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ADT7490 dBCoolR Remote Thermal Monitor and Fan Controller with PECI Interface
The ADT7490 is a dBCool thermal monitor and multiple PWM fan controller for noise-sensitive or power-sensitive applications requiring active system cooling. The ADT7490 includes a local temperature sensor, two remote temperature sensors including series resistance cancellation, and monitors CPU temperature with a PECI interface. The ADT7490 can drive a fan using either a low or high frequency drive signal, and measure and control the speed of up to four fans so they operate at the lowest possible speed for minimum acoustic noise. The automatic fan speed control loop optimizes fan speed for a given temperature using the PECI, remote, or local temperature information. The effectiveness of the system's thermal solution can be monitored using the THERM input. The ADT7490 also provides critical thermal protection to the system using the bidirectional THERM/SMBALERT pin as an output to prevent system or component overheating.
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QSOP-24 NB CASE 492B
MARKING DIAGRAMS
1 ADT7490 ARQZ #DateCode Assembly Lot
* Temperature Measurement
*
* * * * *
1 Local On-Chip Temperature Sensor 2 Remote Temperature Sensors 3 Current External Temperature Sensors with Series Resistance Cancellation (SRC) PECI Interface for CPU Thermal Information and Support of Up to 4 PECI Inputs on 1 Pin Fan Drive and Fan Speed Control 3 High Frequency or Low Frequency PWM Outputs for Use with 3-Wire or 4-Wire Fans 4 TACH Inputs to Measure Fan Speed OS Independent Automatic Fan Speed Control Based on Thermal Information Dynamic TMIN Control Mode to Optimize System Acoustics Default Startup at 100% PWM for All Fans for Robust Operation Bidirectional THERM/SMBALERT Pin to Flag Out-of-Limit and Overtemperature Conditions GPIO Functionality to Support Extra Features Can be Used for Loadline Setting for Voltage Regulation, LED Control, or Other Functions IMON Monitoring for CPU Current and Power Information Footprint and Register Compatible with ADT7473/ADT7475/ ADT7476/ADT7476A Family of Fan Controllers SMBus Interface with Addressing Capability for Up to 3 Devices
TOP MARKING
BOTTOM MARKING
# = Pb-Free Package
PIN ASSIGNMENT
SDA 1 SCL 2 GND 3 VCC 4 GPIO1 5 GPIO2 6 PECI 7 VTT 8 TACH3 9 PWM2/SMBALERT 10 TACH1 11 TACH2 12
24 PWM1/XTO 23 VCCP 22 +2.5V IN/THERM 21 +12V IN 20 +5V IN
ADT7490
TOP VIEW
19 IMON 18 D1+ 17 D1- 16 D2+ 15 D2-
TACH4/THERM/SMBALERT/ ADDR SELECT 13 PWM3/ADDREN
14
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 74 of this data sheet.
Applications
* Personal Computers * Servers
(c) Semiconductor Components Industries, LLC, 2009
December, 2009 - Rev. 4
1
Publication Order Number: ADT7490/D
ADT7490
ADDR SELECT SCL SDA
ADT7490
SMBus ADDRESS SELECTION GPIO REGISTER PERFORMANCE MONITORING THERMAL PROTECTION TACH1 TACH2 TACH3 TACH4 PWM1 PWM2 PWM3 PWM REGISTERS AND CONTROLLERS (HF AND LF) FAN SPEED COUNTER AUTOMATIC FAN SPEED CONTROL ACOUSTIC ENHANCEMENT ADDRESS POINTER REGISTER PWM CONFIGURATION REGISTERS INTERRUPT MASKING SERIAL BUS INTERFACE
GPIO1 GPIO2 THERM/ SMBALERT
DYNAMIC TMIN CONTROL
PECI VTT VCC VCCP +12VIN +5VIN +2.5VIN IMON D1+ D1- D2+ D2- BAND GAP TEMP. SENSOR
PECI INTERFACE INTERRUPT STATUS REGISTERS
ACOUSTIC ENHANCEMENT CONTROL INPUT SIGNAL CONDITIONING AND ANALOG MULTIPLEXER
10-BIT ADC
LIMIT COMPARATORS
BAND GAP REFERENCE
VALUE AND LIMIT REGISTERS
GND
Figure 1. Functional Block Diagram
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ADT7490
ABSOLUTE MAXIMUM RATINGS
Parameter Positive Supply Voltage (VCC) Maximum Voltage on +12 VIN Pin Maximum Voltage on +5 VIN Pin Maximum Voltage on All Open-Drain Outputs (excluding PWM pins) Maximum Voltage on TACHx/PWMx Pins Voltage on Remaining Input or Output Pins Input Current at Any Pin Package Input Current Maximum Junction Temperature (TJ max) Storage Temperature Range Lead Temperature, Soldering IR Reflow Peak Temperature Pb-Free Peak Temperature Lead Temperature (Soldering, 10 sec) ESD Rating HBM FICDM Rating 3.6 16 6.25 3.6 +5.5 -0.3 to +4.2 5 20 150 -65 to +150 220 260 300 2 0.5 Unit V V V V V V mA mA C C C
kV
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.
THERMAL CHARACTERISTICS
Package Type 24-lead QSOP qJA 122 qJC 31.25 Unit C/W
tLOW
SCL
tR
tF
tHD;STA
tHD;STA
tHD;DAT
tHIGH
tSU;DAT
tSU;STA
tSU;STO
SDA P
tBUF
S
S
P
Figure 2. SMBus Bus Timing
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ADT7490
ELECTRICAL CHARACTERISTICS TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. (Note 1)
Parameter Power Supply Supply Voltage Supply Current, ICC Temperature-to-Digital Converter Local Sensor Accuracy Resolution Remote Diode Sensor Accuracy 0C TA 85C -40C TA +125C 0C TA 85C -40C TA +125C Mid level Low level High level The ADT7490 cancels up to 2 kW in series with the remote thermal sensor For all channels: -40C TA +125C For all other channels except +12 VIN: 0C TA +125C 8 bits 0.1 Averaging enabled, all channels excluding VTT (Note ) Averaging enabled Averaging enabled Averaging enabled Averaging enabled Averaging disabled For +12 VIN channel For all other channels 0C TA 85C -40C TA +125C Fan count = 0xBFFF Fan count = 0x3FFF Fan count = 0x0438 Fan count = 0x021C 109 329 5000 10,000 8.0 IOUT = -8.0 mA VOUT = VCC IOUT = -4.0 mA VOUT = VCC 2.0 0.8 500 0.1 0.1 0.4 20 0.4 1.0 150 70 0.5 0.25 0.5 0.25 12 72 192 1.5 1.5 2.5 1.5 2.5 C Interface inactive, ADC active 3.0 3.3 1.5 3.6 5.0 V mA Conditions Min Typ Max Unit
C
Remote Sensor Source Current
mA
Series Resistance Cancellation (Note 2) Total Unadjusted Error (TUE)
kW
Analog-to-Digital Converter (Including MUX and Attentuators) 2 1.5 1 %
Differential Non-linearity (DNL) Power Supply Sensitivity Conversion Times (Note 2) Voltage Inputs VTT Voltage Input (Note 3) Local Temperature Remote Temperature Total Monitoring Cycle Time Input Resistance Fan RPM-to-Digital Converter Accuracy Full-Scale Count Nominal Input RPM
LSB %/V
11 12 12 38 169 19 200 100
13 14 14 43 193
ms
ms kW
10 14 65,535
%
RPM
Open-Drain Digital Outputs, PWM1 TO PWM3, XTO Current Sink, IOL Output Low Voltage, VOL High Level Output Current, IOH Output Low Voltage, VOL High Level Output Current, IOH SMBus Digital Inputs (SCL, SDA) Input High Voltage, VIH Input Low Voltage, VIL Hysteresis V V mV mA V mA V mA
Open-Drain Serial Data Bus Output (SDA)
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ADT7490
ELECTRICAL CHARACTERISTICS TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. (Note 1)
Parameter Digital I/O (PECI Pin) (Note 2) VTT, Supply Voltage Input High Voltage , VIH Input Low Voltage, VIL Hysteresis (Note 2) High Level Output Source Current, ISOURCE Low Level Output Sink Current, ISINK Signal Noise Immunity, VNOISE Hysteresis between input switching levels VOH = 0.75 x VTT VOL = 0.25 x VTT Noise glitches from 10 MHz to 100 MHz, width up to 50 ns 0.5 300 0.1 x VTT (Note 3) 6.0 1.0 0.95 0.55 x VTT (Note 3) 0.5 x VTT (Note 3) 1.26 V V V mV mA mA mV p-p V V V p-p V 0.4 VIN = VCC VIN = 0 (See Figure 2) 10 4.7 4.7 4.0 50 1000 300 250 Can be optionally disabled 15 35 400 50 kHz ns ms ms ms ns ms ns ms 1 1 5.0 V mA mA pF Conditions Min Typ Max Unit
Digital Input Logic Levels (TACH1 to TACH3) Input High Voltage, VIH Input Low Voltage, VIL Hysteresis Digital Input Logic Levels (THERM) Input High Voltage, VIH Input Low Voltage, VIL Digital Input Current Input High Current, IIH Input Low Current, IIL Input Capacitance, CIN Serial Bus Timing (Note 2) Clock Frequency, fSCLK Glitch Immunity, tSW Bus Free Time, tBUF SCL Low Time, tLOW SCL High Time, tHIGH SCL, SDA Rise Time, tr SCL, SDA Fall Time, tf Data Setup Time, tSU;DAT Detect Clock Low Timeout, tTIMEOUT 0.75 x VCCP Maximum input voltage Minimum input voltage 2.0 5.5 0.8 0.5
-0.3
1. All voltages are measured with respect to GND, unless otherwise specified. Typical voltages are TA = 25C and represent a parametric norm. Logic inputs accept input high voltages up to VMAX, even when the device is operating down to VMIN. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge, and VIH = 2.0 V for a rising edge. 2. Guaranteed by design, not production tested. 3. VTT is the voltage input on Pin 8. The VTT voltage is determined by the processor installed on the system.
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ADT7490
PIN ASSIGNMENT
Pin No. 1 2 3 4 5 Mnemonic SDA SCL GND VCC GPIO1 Type Digital I/O Digital Input Ground Power Supply Digital Input/Output Description SMBus Bidirectional Serial Data. Open drain, requires SMBus pullup. SMBus Serial Clock Input. Open drain, requires SMBus pullup. Ground Pin. 3.3 V 10%. General-Purpose Open-Drain Digital Input/Output. Frequently used for switching load line resistors into VR load line circuitry or for switching LEDs using external FETs. General-Purpose Open-Drain Digital Input/Output. Frequently used for switching load line resistors into VR load line circuitry or for switching LEDs using external FETs. PECI Input to Report CPU Thermal Information. PECI voltage level is referenced on the VTT input. Voltage Reference for PECI. This is the supply voltage for the PECI interface and must be present to measure temperature over the PECI interface. This voltage is also monitored and presented in Register 0x1E. Fan Tachometer Input to Measure Speed of Fan 3 (Open-Drain Digital Input). Pulse-Width Modulated Output to Control Fan 2 Speed. Open drain requires 10 kW typical pullup. Digital Output (Open Drain). This pin can be reconfigured as an SMBALERT interrupt output to signal out-of-limit conditions. Fan Tachometer Input to Measure Speed Of Fan 1 (Open-Drain Digital Input). Fan Tachometer Input To Measure Speed Of Fan 2 (Open-Drain Digital Input). Pulse-Width Modulated Output to Control Fan 3 Speed. Open drain requires 10 kW typical pullup. If pulled low on powerup, the ADT7490 enters address select mode, and the state of Pin 14 (ADDR SELECT) determines the ADT7490 slave address. Fan Tachometer Input to Measure Speed of Fan 4 (Open-Drain Digital Input). May be reconfigured as a bidirectional THERM pin. Can be connected to the PROCHOT output of the processor, to time and monitor PROCHOT assertions. Can be used as an output to signal overtemperature conditions or for clock modulation purposes. Active Low Digital Output. The SMBALERT pin is used to signal out-of-limit comparisons of temperature, voltage, and fan speed. This is compatible with SMBus alert. Can also be used at device powerup to assign SMBus address. Negative Connection for Remote Temperature Sensor 2. Positive Connection to Remote Temperature Sensor 2. Negative Connection for Remote Temperature Sensor 1. Positive Connection to Remote Temperature Sensor 1. Monitors Current Output of Analog Devices ADP319x family of VRD10/VRD11 controllers. Monitors 5.0 V Supply Using Internal Resistor Dividers. Monitors 12 V Supply Using Internal Resistor Dividers. Monitors 2.5 V Supply Using Internal Resistor Dividers. Alternatively, this pin can be reconfigured as a bidirectional THERM pin. Can be connected to the PROCHOT output of the processor to time and monitor PROCHOT assertions. Can be used as an output to signal overtemperature conditions or for clock modulation purposes. Monitors CPU VCC Voltage (to maximum of 3.0 V). All voltage inputs can have their resistor dividers removed allowing for full-scale input of 2.25 V of the ADC channel. Pulse-Width Modulated Output to Control Fan 1 Speed. Open drain requires 10 kW typical pullup. Also functions as the output for the XNOR tree test enable mode.
6
GPIO2
Digital Input/Output
7 8
PECI VTT
Digital Input/Output Analog Input
9 10
TACH3 PWM2/SMBALERT
Digital Input Digital Output
11 12 13
TACH1 TACH2 PWM3/ ADDREN
Digital Input Digital Input Digital Output
14
TACH4/THERM/ SMBALERT/ ADDR SELECT
Digital Input/Output
15 16 17 18 19 20 21 22
D2- D2+ D1- D1+ IMON +5 VIN +12 VIN +2.5 VIN/THERM
Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input
23
VCCP
Analog Input
24
PWM1/XTO
Digital Output
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ADT7490
Table 1. Comparison of ADT7490 and ADT7476A Configurations
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SDA SCL GND VCC GPIO1 GPIO2 PECI VTT TACH3 PWM2/SMBALERT TACH1 TACH2 PWM3/ADDREN TACH4/THERM/SMBALERT/ADDR SELECT D2- D2+ D1- D1+ IMON +5 VIN +12 VIN +2.5 VIN/ THERM VCCP PWM1/XTO ADT7490 SDA SCL GND VCC VID0/GPIO0 VID1/GPIO1 VID2/GPIO2 VID3/GPIO3 TACH3 PWM2/SMBALERT TACH1 TACH2 PWM3/ ADDREN TACH4/THERM/SMBALERT/GPIO6/ADDR SELECT D2- D2+ D1- D1+ VID4/GPIO4 +5 VIN +12 VIN/VID5 +2.5 VIN/ THERM VCCP PWM1/XTO ADT7476A
TYPICAL CHARACTERISTICS
4.7 4.24
4.5
4.22 DEV 2
NORMAL IDD (mA)
DEV 1 DEV 3 DEV 2
4.1
NORMAL IDD (mA)
4.3
4.20
4.18 DEV 1
3.9
4.16
3.7
4.14
DEV 3
3.5 3.0
3.1
3.2
3.3 VDD (V)
3.4
3.5
3.6
4.12 -40
-20
0
20
40
60
80
100
120
TEMPERATURE (5C)
Figure 3. Supply Current vs. Supply Voltage
Figure 4. Supply Current vs. Temperature
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ADT7490
TYPICAL CHARACTERISTICS
3.0 2.5 TEMPERATURE ERROR (5C) 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -40 -20 0 25 40 60 70 85 100 125
DEV 1 DEV 2 DEV 3 DEV 4 DEV 5 DEV 6 DEV 7 DEV 8 DEV 9 DEV 10 DEV 11 DEV 12 DEV 13 DEV 14 DEV 15 DEV 16 DEV 17 DEV 18 DEV 19 DEV 20 DEV 21 DEV 22 DEV 23 DEV 24 DEV 25 DEV 26 DEV 27 DEV 28 DEV 29 DEV 30 DEV 31 DEV 32 MEAN LOW SPEC HIGH SPEC
3.0 2.5 TEMPERATURE ERROR (5C) 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -40 -20 0 25 40 60 70 85 100 125
DEV 1 DEV 2 DEV 3 DEV 4 DEV 5 DEV 6 DEV 7 DEV 8 DEV 9 DEV 10 DEV 11 DEV 12 DEV 13 DEV 14 DEV 15 DEV 16 DEV 17 DEV 18 DEV 19 DEV 20 DEV 21 DEV 22 DEV 23 DEV 24 DEV 25 DEV 26 DEV 27 DEV 28 DEV 29 DEV 30 DEV 31 DEV 32 MEAN LOW SPEC HIGH SPEC
TEMPERATURE (5C)
TEMPERATURE (5C)
Figure 5. Local Temperature Sensor Error
Figure 6. Remote 1 Temperature Sensor Error
3.0 2.5 TEMPERATURE ERROR (5C) 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -40 -20 0 25 40 60 70 85 100 125
DEV 1 DEV 2 DEV 3 DEV 4 DEV 5 DEV 6 DEV 7 DEV 8 DEV 9 DEV 10 DEV 11 DEV 12 DEV 13 DEV 14 DEV 15 DEV 16 DEV 17 DEV 18 DEV 19 DEV 20 DEV 21 DEV 22 DEV 23 DEV 24 DEV 25 DEV 26 DEV 27 DEV 28 DEV 29 DEV 30 DEV 31 DEV 32 MEAN LOW SPEC HIGH SPEC
140 120
EXTERNAL 2
MEASURED TEMPERATURE (5C)
EXTERNAL 1 100 80 60 40 20 0 LOCAL
0
10
20
30 TIME (s)
40
50
60
TEMPERATURE (5C)
Figure 7. Remote 2 Temperature Sensor Error
Figure 8. ADT7490 Response to Thermal Shock
8 6 TEMPERATURE ERROR (5C) 4 2 0 DEV 3 -2 -4 DEV 2 -6 -8
4.0 3.5
100mV 250mV
DEV 1 TEMPERATURE ERROR (5C)
3.0 2.5 2.0 1.5 1.0 0.5 0 -0.5
0
200
400
600
800
1000
1200
1400
1600
-1.0
0
100
200
300
400
500
600
SERIES RESISTANCE ()
POWER SUPPLY NOISE FREQUENCY (MHz)
Figure 9. Temperature Error vs. Series Resistance
Figure 10. Local Temperature Error vs. Power Supply Noise Frequency
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ADT7490
TYPICAL CHARACTERISTICS
0.6 0.4 TEMPERATURE ERROR (5C) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 100mV 250mV 15 TEMPERATURE ERROR (5C) 20
10
100mV 60mV 40mV
5
0
-5
0
100
200
300
400
500
600
-10
0
100
200
300
400
500
600
POWER SUPPLY NOISE FREQUENCY (MHz)
COMMON-MODE NOISE FREQUENCY (MHz)
Figure 11. Remote Temperature Error vs. Power Supply Noise Frequency
Figure 12. Temperature Error vs. Common-Mode Noise Frequency
160 140 TEMPERATURE ERROR (5C) TEMPERATURE ERROR (5C) 120 100 80 60 40 20 0 40mV -20 0 100 200 300 400 500 600 60mV
5 0 DEV 3 -5 -10 -15 -20 -25 -30 -35 DEV 2
DEV 1
100mV
0
2
4
6
8
10
12
14
16
18
20
22
DIFFERENTIAL MODE NOISE FREQUENCY (MHz)
CAPACITANCE (nF)
Figure 13. Temperature Error vs. Differential Mode Noise Frequency
Figure 14. Temperature Error vs. Capacitance Between D+ and D-
1.5 1.0 0.5 ACCURACY (%) 0 -0.5 -1.0 DEV 3 ACCURACY (%) DEV 2 DEV 1
8 6 4 2 DEV 2 0 -2 -4 DEV 1 DEV 3
-1.5 -2.0 3.0
-6 3.1 3.2 3.3 VDD (V) 3.4 3.5 3.6 -8 -40 -20 0 20 40 60 80 100 120
TEMPERATURE (5C)
Figure 15. TACH Accuracy vs. Supply Voltage
Figure 16. TACH Accuracy vs. Temperature
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ADT7490
Theory of Operation The ADT7490 is a complete thermal monitor and multiple fan controller for any system requiring thermal monitoring and cooling. The device communicates with the system via a serial system management bus. The serial bus controller has a serial data line for reading and writing addresses and data (Pin 1), and an input line for the serial clock (Pin 2). All control and programming functions for the ADT7490 are performed over the serial bus. In addition, Pin 14 can be reconfigured as an SMBALERT output to signal out-of-limit conditions.
Feature Comparisons Between the ADT7490 and ADT7476A Temperature Data REPLACE Mode
The REPLACE mode is configured by setting Bit 4 of Register 0x36. In this mode, the data in the existing Remote 1 registers are replaced by PECI0 data and vice versa. This is a legacy mode that allows the thermal data from CPU1 to be stored in the same registers as in the ADT7476A. This reduces the software changes in systems transitioning from CPUs with thermal diodes to CPUs with a PECI interface. See the PECI Temperature Measurement section for more details.
Fan Control Using PECI Information
The ADT7490 is pin and register map compatible with the ADT7476A. The new or additional features are detailed in the following sections.
PECI Input
CPU thermal information is provided through the PECI input. The ADT7490 has PECI master capabilities and can read the CPU thermal information through the PECI interface. Each CPU address can have up to two PECI domains. The ADT7490 has the ability to record four PECI temperature readings corresponding to the four PECI addresses of 0x30 to 0x33. The hotter of the two domains at any given address is stored in the PECI value registers. A PECI reading is a negative value, in degrees Celsius, which represents the offset from the thermal control circuit (TCC) activation temperature. PECI information is not converted to absolute temperature reading. PECI information is in a 16-bit twos complement value; however, the ADT7490 records the sign bit as well as the bits from 12:6 in the 16-bit PECI payload. See the Platform Environment Control Interface (PECI) Specification from Intel(R) for more details on the PECI data format. The PECI format is represented in Table 2.
Table 2. PECI Data Format
MSB Upper Nibble S x x x x Sign Bit MSB Lower Nibble x x x Integer value (0C to 127C)
The CPU thermal information from PECI can be used in the existing automatic fan control algorithms. This temperature reading remains relative to TCC activation temperature and the associated AFC control parameters are programmed in relative temperatures as opposed to absolute temperatures, and are in the same format as detailed in Table 2. PECIMIN, TRANGE, and TCONTROL are user defined.
PWM = 100% PWMMAX
PWMMIN TRANGE PWM = 0% PECIMIN (TMIN) (TMAX)
PECI = 0 TCC TCONTROL
Figure 17. Overview of Automatic Fan Speed Control Using PECI Thermal Information Dynamic TMIN Fan Control Mode
There are associated high and low limits for each PECI reading that can be programmed. The limit values take the same format as the PECI reading. Therefore, the programmed limits are not absolute temperatures but a relative offset in degrees Celsius from the TCC activation temperature. An out-of-limit event is recorded as follows: * High Limit > comparison performed * Low Limit comparison performed An out-of-limit event is recorded in the associated status register and can be used to assert the SMBALERT pin.
The automatic fan speed control incorporates a feature called dynamic TMIN control. This intelligent fan control feature reduces the design effort required to program the automatic fan speed control loop and improves the system acoustics. The VTT voltage is monitored on Pin 8. This voltage is also used as the reference voltage for the PECI interface. The VTT voltage must be connected to the ADT7490 in order for the PECI interface to be operational.
IMON Monitoring VTT Input
The IMON input on Pin 19 can be used to monitor the IMON output of ON Semiconductor's VR10/VR11.1 controllers.
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ADT7490
IMON is a voltage representation of the CPU current. Using the IMON value and the measured VCCP value on Pin 23, the CPU power consumption can be calculated. See the appropriate Analog Devices flex mode data sheet for calculations. The IMON information can be considered as an early indication of an increase in CPU temperature.
Startup Operation
At startup, the ADT7490 turns the fans on to 100% PWM. This allows the most robust operation at turn-on.
Serial Bus Interface
Control of the ADT7490 is carried out using the serial system management bus (SMBus). The ADT7490 is connected to this bus as a slave device, under the control of a master controller. The ADT7490 has a 7-bit serial bus address. When the device is powered up with Pin 13 (PWM3/ADDREN) high, the ADT7490 has a default SMBus address of 0101110 or 0x2E. The read/write bit must be added to obtain the 8-bit address. If more than one ADT7490 is to be used in a system, each ADT7490 is placed in address select mode by strapping Pin 13 low on powerup. The logic state of Pin 14 then determines the device's SMBus address. The logic of these pins is sampled on powerup. The device address is monitored from powerup but not latched until the first valid SMBus transaction, more precisely on the low-to-high transition at the beginning of the eighth SCL pulse, when the serial bus address byte matches the selected slave address. The selected slave address is chosen using the ADDREN/ADDR SELECT pins. Any attempted changes in the address have no effect after this.
Table 3. Hard-wiring the ADT7490 SMBus Device Address
Pin 13 State 0 0 1 Pin 14 State Low (10 kW to GND) High (10 kW pullup) Don't care Address 0101100 (0x2C) 0101101 (0x2D) 0101110 (0x2E)
Data is sent over the serial bus in sequences of nine clock pulses: eight bits of data followed by an acknowledge bit from the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-to-high transition when the clock is high may be interpreted as a stop signal. The number of data bytes that can be transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle.
When all data bytes have been read or written, stop conditions are established. In write mode, the master pulls the data line high during the 10th clock pulse to assert a stop condition. In read mode, the master device overrides the acknowledge bit by pulling the data line high during the low period before the ninth clock pulse; this is known as no acknowledge. The master takes the data line low during the low period before the 10th clock pulse, and then high during the 10th clock pulse to assert a stop condition. Any number of bytes of data can be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation. In the ADT7490, write operations contain either one or two bytes, and read operations contain one byte. To write data to one of the device data registers or read data from it, the address pointer register must be set so that the correct data register is addressed. Then data can be written into that register or read from it. The first byte of a write operation always contains an address that is stored in the address pointer register. If data is to be written to the device, the write operation must contain a second data byte that is written to the register selected by the address pointer register. This write operation is shown in Figure 18. The device address is sent over the bus, and then R/W is set to 0. This is followed by two data bytes. The first data byte is the address of the internal data register to be written to, which is stored in the address pointer register. The second data byte is the data to be written to the internal data register. When reading data from a register, there are two possibilities: * If the ADT7490 address pointer register value is unknown or not the desired value, it must first be set to the correct value before data can be read from the desired data register. This is done by performing a write to the ADT7490 as before, but only the data byte containing the register address is sent because no data is written to the register. This is shown in Figure 19. A read operation is then performed consisting of the serial bus address, R/W bit set to 1, followed by the data byte read from the data register. This is shown in Figure 20. * If the address pointer register is known to be already at the desired address, data can be read from the corresponding data register without first writing to the address pointer register, as shown in Figure 20.
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ADT7490
1 SCL 9 1 9
SDA START BY MASTER
0
1
0
1
1
1
0
R/W ACK. BY ADT7490
D7
D6
D5
D4
D3
D2
D1
D0 ACK. BY ADT7490
FRAME 1 SERIAL BUS ADDRESS BYTE
FRAME 2 ADDRESS POINTER REGISTER BYTE 9
1 SCL (CONTINUED)
SDA (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0 ACK. BY ADT7490 STOP BY MASTER
FRAME 3 DATA BYTE
Figure 18. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register
1 SCL 9 1 9
SDA START BY MASTER
0
1
0
1
1
1
0
R/W ACK. BY ADT7490
D7
D6
D5
D4
D3
D2
D1
D0 ACK. BY ADT7490 STOP BY MASTER
FRAME 1 SERIAL BUS ADDRESS BYTE
FRAME 2 ADDRESS POINTER REGISTER BYTE
Figure 19. Writing to the Address Pointer Register Only
1 SCL 9 1 9
SDA START BY MASTER
0
1
0
1
1
1
0
R/W ACK. BY ADT7490
D7
D6
D5
D4
D3
D2
D1
D0 NO ACK. BY STOP BY MASTER MASTER
FRAME 1 SERIAL BUS ADDRESS BYTE
FRAME 2 DATA BYTE FROM ADT7490
Figure 20. Reading Data from a Previously Selected Register
It is possible to read a data byte from a data register without first writing to the address pointer register if the address pointer register is already at the correct value. However, it is not possible to write data to a register without writing to the address pointer register because the first data byte of a write is always written to the address pointer register. In addition to supporting the send byte and receive byte protocols, the ADT7490 also supports the read byte protocol (see System Management Bus Specifications Rev. 2 for more information; this document is available from the SMBus organization). If several read or write operations must be performed in succession, the master can send a repeat start condition instead of a stop condition to begin a new operation.
Write Operations
in the ADT7490 are discussed here. The following abbreviations are used in the diagrams: * S: Start * P: Stop * R: Read * W: Write * A: Acknowledge * A: No acknowledge The ADT7490 uses the following SMBus write protocols.
Send Byte
The SMBus specification defines several protocols for different types of read and write operations. The ones used
In this operation, the master device sends a single command byte to a slave device, as follows: 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the write bit (low). 3. The addressed slave device asserts ACK on SDA.
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4. The master sends a command code. 5. The slave asserts ACK on SDA. 6. The master asserts a stop condition on SDA and the transaction ends. For the ADT7490, the send byte protocol is used to write a register address to RAM for a subsequent single-byte read from the same address. This operation is illustrated in Figure 21.
1 2 3 4 REGISTER ADDRESS 56 AP SLAVE S WA ADDRESS
previously been set by a send byte or write byte operation. This operation is illustrated in Figure 23.
1 2 3 4 DATA 56 AP SLAVE S ADDRESS R A
Figure 23. Single-Byte Read from a Register Alert Response Address
Figure 21. Setting a Register Address for Subsequent Read
If the master is required to read data from the register immediately after setting up the address, it can assert a repeat start condition immediately after the final ACK and carry out a single-byte read without asserting an intermediate stop condition.
Write Byte
In this operation, the master device sends a command byte and one data byte to the slave device, as follows: 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the write bit (low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends a command code. 5. The slave asserts ACK on SDA. 6. The master sends a data byte. 7. The slave asserts ACK on SDA. 8. The master asserts a stop condition on SDA, and the transaction ends. The byte write operation is illustrated in Figure 22.
1 2 3 4 REGISTER ADDRESS 5 A 6 7 8 SLAVE S ADDRESS W A DATA A P
Alert response address (ARA) is a feature of SMBus devices that allows an interrupting device to identify itself to the host when multiple devices exist on the same bus. The SMBALERT output can be used as either an interrupt output or an SMBALERT. One or more outputs can be connected to a common SMBALERT line connected to the master. If a device's SMBALERT line goes low, the following events occur: 1. SMBALERT is pulled low. 2. The master initiates a read operation and sends the alert response address (ARA = 0001 100). This is a general call address that must not be used as a specific device address. 3. The device whose SMBALERT output is low responds to the alert response address, and the master reads its device address. The address of the device is now known and can be interrogated in the usual way. 4. If more than one device's SMBALERT output is low, the one with the lowest device address has priority in accordance with normal SMBus arbitration. 5. Once the ADT7490 has responded to the alert response address, the master must read the status registers, and the SMBALERT is cleared only if the error condition is gone.
SMBus Timeout
Figure 22. Single Byte Write to a Register Read Operations
The ADT7490 uses the following SMBus read protocols.
Receive Byte
The ADT7490 includes an SMBus timeout feature. If there is no SMBus activity for 35 ms, the ADT7490 assumes the bus is locked and releases the bus. This prevents the device from locking or holding the SMBus expecting data. Some SMBus controllers cannot work with the SMBus timeout feature, so it can be disabled.
Configuration Register 7 (Register 0x11)
This operation is useful when repeatedly reading a single register. The register address must be previously set up. In this operation, the master device receives a single byte from a slave device, as follows: 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the read bit (high). 3. The addressed slave device asserts ACK on SDA. 4. The master receives a data byte. 5. The master asserts NO ACK on SDA. 6. The master asserts a stop condition on SDA, and the transaction ends. In the ADT7490, the receive byte protocol is used to read a single byte of data from a register whose address has
Bit 4 (TODIS) = 0, SMBus timeout enabled (default) Bit 4 (TODIS) = 1, SMBus timeout disabled
Voltage Measurement Input
The ADT7490 has six external voltage measurement channels. It can also measure its own supply voltage, VCC. Pin 20 to Pin 23 can measure 5.0 V, 12 V, and 2.5 V supplies, and the processor core voltage VCCP (0 V to 3.0 V input). The 2.5 V input can be used to monitor a chipset supply voltage in computer systems. The VCC supply voltage measurement is carried out through the VCC pin (Pin 4). Pin 8 measures the VTT voltage of the processor and
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is the dedicated reference voltage for the PECI circuitry. The IMON input on Pin 19 can be used to monitor the IMON output of ON Semiconductor's VR11.1 controllers. IMON is a voltage representation of the CPU current.
Analog-to-Digital Converter Voltage Limit Registers
All analog inputs are multiplexed into the on-chip, successive approximation, analog-to-digital converter. This ADC has a resolution of 10 bits. The basic input range is 0 V to 2.25 V, but the inputs have built-in attenuators to allow measurement of 2.5 V, 3.3 V, 5.0 V, 12 V, and the processor core voltage VCCP without any external components. To allow the tolerance of these supply voltages, the ADC produces an output of 3/4 full scale (768 decimal or 0x300 hexadecimal) for the nominal input voltage, and therefore, has adequate headroom to cope with overvoltages.
Input Circuitry
Associated with each voltage measurement channel is a high and low limit register. Exceeding the programmed high or low limit causes the appropriate status bit to be set. Exceeding either limit can also generate SMBALERT interrupts.
Register 0x85, IMON Low Limit = 0x00 default
The internal structure for the analog inputs is shown in Figure 24 . The input circuit consists of an input protection diode, an attenuator, plus a capacitor to form a first-order low-pass filter that gives input immunity to high frequency noise.
Voltage Measurement Registers
Register 0x87, IMON High Limit = 0xFF default Register 0x84, VTT Low Limit = 0x00 default Register 0x86, VTT High Limit = 0xFF default Register 0x44, +2.5 VIN Low Limit = 0x00 default Register 0x45, +2.5 VIN High Limit = 0xFF default Register 0x46, VCCP Low Limit = 0x00 default Register 0x47, VCCP High Limit = 0xFF default Register 0x48, VCC Low Limit = 0x00 default Register 0x49, VCC High Limit = 0xFF default Register 0x4A, +5 VIN Low Limit = 0x00 default Register 0x4B, +5 VIN High Limit = 0xFF default Register 0x4C, +12 VIN Low Limit = 0x00 default Register 0x4D, +12 VIN High Limit = 0xFF default
Register 0x1D, IMON Reading = 0x00 default Register 0x1E, VTT Reading = 0x00 default Register 0x20, +2.5 VIN Reading = 0x00 default Register 0x21, VCCP Reading = 0x00 default Register 0x22, VCC Reading = 0x00 default Register 0x23, +5 VIN Reading = 0x00 default Register 0x24, +12 VIN Reading = 0x00 default
+12VIN 120kW 20k W 30pF
When the ADC is running, it samples and converts a voltage input in 0.7 ms and averages 16 conversions to reduce noise; a measurement takes nominally 11 ms.
Extended Resolution Registers
Voltage measurements can be made with higher accuracy using the extended resolution registers (0x1F, 0x76, and 0x77). Whenever the extended resolution registers are read, the corresponding data in the voltage measurement registers (0x1D, 0x1E, and 0x20 to 0x24) is locked until their data is read. That is, if extended resolution is required, the extended resolution register must be read first, immediately followed by the appropriate voltage measurement register.
Additional ADC Functions for Voltage Measurements
+5VIN
93k W 47k W 30pF
VCC
68k W 71k W 45k W 94k W 17.5kW 52.5k W 45k W 94k W 45k W 45k W 30pF 30pF 35pF 30pF MUX 30pF
A number of other functions are available on the ADT7490 to offer the system designer increased flexibility. The functions described in the following sections are enabled by setting the appropriate bit in Configuration Register 2.
Configuration Register 2 (Register 0x73)
+2.5VIN
VCCP
Bit 4 (AVG) = 1, averaging off. Bit 5 (ATTN) = 1, bypass input attenuators. Bit 6 (CONV) = 1, single-channel convert mode.
Turn-Off Averaging
IMON
VTT
Figure 24. Analog Inputs Structure
For each voltage/temperature measurement read from a value register, 16 readings have actually been made internally and the results averaged before being placed into the value register. When faster conversions are needed, setting Bit 4 (AVG) of Configuration Register 2 (0x73) turns averaging off. This effectively gives a reading that is 16 times faster, but the reading can be noisier. The default round-robin cycle time takes 146.5 ms.
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Table 4. Conversion Time with Averaging Disabled
Channel Voltage Channels Remote Temperature 1 Remote Temperature 2 Local Temperature Measurement Time (ms) 0.7 7 7 1.3
Single-Channel ADC Conversion
When Bit 7 (ExtraSlow) of Configuration Register 6 (0x10) is set, the default round-robin cycle time increases to 240 ms.
Bypass All Voltage Input Attenuators
While single-channel mode is intended as a test mode that can be used to increase sampling times for a specific channel, therefore helping to analyze that channel's performance in greater detail, it can also have other applications. Setting Bit 6 of Configuration Register 2 (0x73) places the ADT7490 into single-channel ADC conversion mode. In this mode, the ADT7490 can read a single voltage channel only. The selected voltage input is read every 0.7 ms. The appropriate ADC channel is selected by writing to Bits [7:4] of the TACH1 minimum high byte register (0x55).
Table 6. Programming Single-Channel ADC Mode
Bits [7:4], Register 0x55 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 Channel Selected (Note 1) +2.5 VIN VCCP VCC +5 VIN +12 VIN Remote 1 temperature Local temperature Remote 2 temperature VTT IMON
Setting Bit 5 of Configuration Register 2 (0x73) removes the attenuation circuitry from the 2.5 VIN, VCCP, VCC, 5 VIN, and 12 VIN inputs. This allows the user to directly connect external sensors or rescale the analog voltage measurement inputs for other applications. The input range of the ADC without the attenuators is 0 V to 2.25 V.
Bypass Individual Voltage Input Attenuators
Bits [7:4] of Configuration Register 4 (0x7D) can be used to bypass individual voltage channel attenuators.
Table 5. Bypassing Individual Voltage Input Attenuators
Configuration Register 4 (0x7D) Bit No. 4 5 6 7 Channel Attenuated Bypass +2.5 VIN attenuator Bypass VCCP attenuator Bypass +5 VIN attenuator Bypass +12 VIN attenuator
1. In the process of configuring single-channel ADC conversion mode, the TACH1 minimum high byte is also changed, possibly trading off TACH1 minimum high byte functionality with single-channel mode functionality.
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Table 7. 10-Bit ADC Output Code vs. VIN
Input Voltage +12 VIN <0.0156 0.0156 to 0.0312 0.0312 to 0.0469 0.0469 to 0.0625 0.0625 to 0.0781 0.0781 to 0.0937 0.0937 to 0.1093 0.1093 to 0.1250 0.1250 to 0.14060 - 4.0000 to 4.0156 - 8.0000 to 8.0156 - 12.0000 to 12.0156 - 15.8281 to 15.8437 15.8437 to 15.8593 15.8593 to 15.8750 15.8750 to 15.8906 15.8906 to 15.9062 15.9062 to 15.9218 15.9218 to 15.9375 15.9375 to 15.9531 15.9531 to 15.9687 15.9687 to 15.9843 >15.9843 +5 VIN <0.0065 0.0065 to 0.0130 0.0130 to 0.0195 0.0195 to 0.0260 0.0260 to 0.0325 0.0325 to 0.0390 0.0390 to 0.0455 0.0455 to 0.0521 0.0521 to 0.0586 - 1.6675 to 1.6740 - 3.3300 to 3.3415 - 5.0025 to 5.0090 - 6.5983 to 6.6048 6.6048 to 6.6113 6.6113 to 6.6178 6.6178 to 6.6244 6.6244 to 6.6309 6.6309 to 6.6374 6.6374 to 6.4390 6.6439 to 6.6504 6.6504 to 6.6569 6.6569 to 6.6634 >6.6634 VCC (3.3 VIN) <0.0042 0.0042 to 0.0085 0.0085 to 0.0128 0.0128 to 0.0171 0.0171 to 0.0214 0.0214 to 0.0257 0.0257 to 0.0300 0.0300 to 0.0343 0.0343 to 0.0386 - 1.1000 to 1.1042 - 2.2000-2.204 2 - 3.3000 to 3.3042 - 4.3527 to 4.3570 4.3570 to 4.3613 4.3613 to 4.3656 4.3656 to 4.3699 4.3699 to 4.3742 4.3742 to 4.3785 4.3785 to 4.3828 4.3828 to 4.3871 4.3871 to 4.3914 4.3914 to 4.3957 >4.3957 +2.5 VIN <0.0032 0.0032 to 0.0065 0.0065 to 0.0097 0.0097 to 0.0130 0.0130 to 0.0162 0.0162 to 0.0195 0.0195 to 0.0227 0.0227 to 0.0260 0.0260 to 0.0292 - 0.8325 to 0.8357 - 1.6650 to 1.6682 - 2.4975 to 2.5007 - 3.2942 to 3.2974 3.2974 to 3.3007 3.3007 to 3.3039 3.3039 to 3.3072 3.3072 to 3.3104 3.3104 to 3.3137 3.3137 to 3.3169 3.3169 to 3.3202 3.3202 to 3.3234 3.3234 to 3.3267 >3.3267 VCCP <0.00293 0.0293 to 0.0058 0.0058 to 0.0087 0.0087 to 0.0117 0.0117 to 0.0146 0.0146 to 0.0175 0.0175 to 0.0205 0.0205 to 0.0234 0.0234 to 0.0263 - 0.7500 to 0.7529 - 1.5000 to 1.5029 - 2.2500 to 2.2529 - 2.9677 to 2.9707 2.9707 to 2.9736 2.9736 to 2.9765 2.9765 to 2.9794 2.9794 to 2.9824 2.9824 to 2.9853 2.9853 to 2.9882 2.9882 to 2.9912 2.9912 to 2.9941 2.9941 to 2.9970 >2.9970 VTT/IMON <0.00220 0.00220 to 0.00440 0.00440 to 0,00660 0,00660 to 0.00881 0.00881 to 0.01100 0.01100 to 0.01320 0.01320 to 0.01541 0.01541 to 0.01761 0.01761 to 0.01981 - 0.5636 to 0.5658 - 1.1272 to 1.1294 - 1.6809 to 1.6930 - 2.2301 to 2.2323 2.2323 to 2.2346 2.2346 to 2.2368 2.2368 to 2.23899 2,23899 to 2.2412 2.2412 to 2.2434 2.2434 to 2.2456 2.2456 to 2.2478 2.2478 to 2.25 2.25 to 2.2522 >2.2522 0 1 2 3 4 5 6 7 8 - 256
(1/4 scale)
ADC Output Decimal Binary (10 Bits) 00000000 00 00000000 01 00000000 10 00000000 11 00000001 00 00000001 01 00000001 10 00000001 11 00000010 00 - 01000000 00 - 10000000 00 - 11000000 00 - 11111101 01 11111101 10 11111101 11 11111110 00 11111110 01 11111110 10 11111110 11 11111111 00 11111111 01 11111111 10 1111111111 1
- 512
(1/2 scale)
- 768
(3/4 scale)
- 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023
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Temperature Measurement PECI Offset Registers
The ADT7490 has four temperature measurement channels: one local, two remote thermal diodes, and a PECI. The local and thermal diode readings are analog temperature measurements, whereas PECI is a digital temperature reading.
PECI Temperature Measurement
Each PECI reading has a dedicated offset register to calibrate the PECI measurement and account for errors in the temperature reading. The LSBs add a 1C offset to the temperature reading so that the 8-bit register effectively allows temperature offsets of up to 128C with a resolution of 1C.
Register 0x94, PECI0 Offset Register 0x95, PECI1 Offset Register 0x96, PECI2 Offset Register 0x97, PECI3 Offset
PECI Data Smoothing
The PECI interface is a dedicated thermal interface. The CPU temperature measurement is carried out internally in the CPU. This information is digitized and transferred to the ADT7490 via the PECI interface. The ADT7490 is a PECI host device and therefore, polls the CPU for thermal information. The PECI measurement differs from traditional thermal diode temperature measurements in that the measurement is a relative value instead of an absolute value. The PECI reading is a negative value that indicates how close the CPU temperature is from the thermal throttling or TCC point of the CPU. The ADT7490 records and uses the PECI measurement for fan control in its relative format. Therefore, care must be taken in programming the relevant limits and fan control parameters in the PECI format. Refer to the PECI Input section and Table 2 for further PECI information. PECI monitoring is enabled on the ADT7490 by setting the PECI monitoring bit in Configuration Register 1 (Register 0x40, Bit 4). The ADT7490 can measure the temperature of up to four dual-core CPUs. The number of CPUs in the system that provide PECI information is set in Bits [7:6] of Register 0x88. Each CPU is distinguished by the PECI address. The number of domains, or domain count, per CPU address must also be programmed into the ADT7490. The ADT7490 reads the temperature of both domains per CPU, however, only the PECI value of the hottest domain is recorded in the PECI value register.
PECI0 domains: Register 0x36, Bit 3 PECI1 domains: Register 0x88, Bit 5 PECI2 domains: Register 0x88, Bit 4 PECI3 domains: Register 0x88, Bit 3
PECI Reading Registers
The PECI smoothing interval is programmed in PECI Configuration Register 1 (0x36). Bits [2:0] of Register 0x36 set the duration over which the PECI data being read by the ADT7490 is averaged. These bits set the duration over which smoothing is carried out on the PECI data read. The refresh rate in the PECI value registers is the same as the smoothing interval programmed. The smoothing interval is calculated using the following formula:
Smoothing Interval + #reads t BIT 67 #CPU ) t IDLE
(eq. 1)
where: #reads is the number of readings defined in Register 0x36, Bits [2:0]. tBIT is the negotiated bit rate. 67 is the number of bits in each PECI reading. #CPU is the number of CPUs providing PECI data (1 to 4). tIDLE = 14 ms, the delay between consecutive reads. For example, #reads = 4096 tBIT = 1 ms (1 MHz speed) #CPU = 1 Smoothing Interval = 331 ms = PECI reading refresh rate
PECI Error Codes
Register 0x33, PECI0: PECI reading from CPU Address 0x30 Register 0x1A, PECI1: PECI reading from CPU Address 0x31 Register 0x1B, PECI2: PECI reading from CPU Address 0x32 Register 0x1C, PECI3: PECI reading from CPU Address 0x33
PECI Limit Registers
Each PECI measurement shares the same high and low limits.
Register 0x34, PECI Low Limit = 0x81 default Register 0x35, PECI High Limit = 0x00 default
There are two different error conditions for PECI data, PECI data errors, and PECI bus communications errors. Table 8 describes the two different error conditions. If the ADT7490 reads an error code (0x8000 to 0x8003) from the CPU over the PECI interface, Bit 1 is set in Interrupt Status 3 register (0x43), indicating a data error. The value of the error code is not included in the PECI value averaging sum. This means that a value of 0x00 is added to the PECI sum when an error code is recorded. The error code is not reported in the appropriate PECI value register. If an invalid FCS is recorded by the ADT7490, Bit 2 is set in the Interrupt Status 3 register (0x43), indicating a communications error. An alert is generated on the SMBALERT pin when either or both of these status bits are asserted.
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Table 8. PECI Error Indicators
PECI Data 0x8000 to 0x8003 Invalid FCS Description PECI data error PECI communications error Action Bit 1 of Register 0x43 is set to 1 Bit 2 of Register 0x43 is set to 1
Table 10. Replace Mode Temperature Registers
Register Name Value Register Low Limit High Limit TMIN TRANGE Enhanced Acoustics Enhanced Acoustics Enable Remote 1 Default Reg. 0x25 Reg. 0x4E Reg. 0x4F Reg. 0x67 Reg. 0x5F, Bits [7:4] Reg. 0x62, Bits [2:0] Reg. 0x62, Bit 3 Reg. 0x6A Reg. 0x6D, Bits [7:4] Reg. 0x6D, Bits [3:0] (Note 1) Reg. 0x70 Reg. 0x8B PECI0 Default Reg. 0x33 Reg. 0x34 Reg. 0x35 Reg. 0x3B Reg. 0x3C, Bits [7:4] Reg. 0x3C, Bits [2:0] Reg. 0x3C, Bit 3 Reg. 0x3D Reg. 0x6E, Bits [3:0] Reg. 0x6E, Bits [7:4] (Note 1) Reg. 0x94 Reg. 0x8A
Each PECI channel also has an associated status bit to indicate if the PECI high or low limits have been exceeded. An alert is generated on the SMBALERT pin when these status bits are asserted.
Table 9. PECI Status Bits
Channel PECI0 PECI1 PECI2 PECI3 Register 0x43 0x81 0x81 0x81 Bit 0 3 4 5
THERM TCONTROL TMIN Hysteresis
Temperature offset Operating Point for Dynamic TMIN
Temperature Data REPLACE Mode
The REPLACE mode is configured by setting Bit 4 of Register 0x36. In this mode, the data in the existing Remote 1 registers are replaced by PECI0 data. This is a legacy mode that allows the thermal data from CPU1 to be stored in the same registers as in the ADT7476A. This reduces the software changes in systems transitioning from CPUs with thermal diodes to CPUs with a PECI interface. However, note that even though the associated registers are swapped, the correct data format (PECI vs. absolute temperature, see Table 2) must be written to and interpreted from these registers.
Notes
1. In REPLACE mode, the Remote 2 and local temperature hysteresis values are swapped.
In REPLACE mode, the temperature zone controlling the relevant PWM output are also swapped from Remote 1 to PECI0. The swap of control only occurs if the default behavior setting for Register 0x5C Bits [7:5], Register 0x5D Bits [7:5] or Register 0x5E Bits [7:5] is 000.
Local Temperature Measurement
In Table 10, registers listed under the Remote 1 Default column are in absolute temperature format by default and are in PECI format in REPLACE mode. Registers listed under the PECI0 Default column are in PECI format by default and in absolute temperature format in REPLACE mode.
The ADT7490 contains an on-chip band gap temperature sensor whose output is digitized by the on-chip 10-bit ADC. The 8-bit MSB temperature data is stored in the local temperature register (Address 0x26). Because both positive and negative temperatures can be measured, the temperature data is stored in Offset 64 format or twos complement format, as shown in Table 11 and Table 12. Theoretically, the temperature sensor and ADC can measure temperatures from -128C to +127C (or -64C to +191C in the extended temperature range) with a resolution of 0.25C. However, this exceeds the operating temperature range of the device, so local temperature measurements outside the ADT7490 operating temperature range are not possible.
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Table 11. Twos Complement Temperature Data Format
Temperature -128C -63C -50C -25C -10C 0C 10.25C 25.5C 50.75C 75C 100C 125C 127C Digital Output (10-Bit) (Note 1) 1000 0000 00 (diode fault) 1100 0001 00 1100 1110 00 1110 0111 00 1111 0110 00 0000 0000 00 0000 1010 01 0001 1001 10 0011 0010 11 0100 1011 00 0110 0100 00 0111 1101 00 0111 1111 00 ADT7490
D+ 2N3906 PNP D- 2N3904 NPN D+ D-
If a discrete transistor is used, the collector is not grounded and should be linked to the base. If a PNP transistor is used, the base is connected to the D- input and the emitter to the D+ input. If an NPN transistor is used, the emitter is connected to the D- input and the base to the D+ input. Figure 25 and Figure 26 show how to connect the ADT7490 to an NPN or PNP transistor for temperature measurement.
ADT7490
Figure 25. Measuring Temperature Using an NPN Transistor
1. Bold numbers denote 2 LSBs of measurement in the Extended Resolution 2 register (Register 0x77) with 0.25C resolution.
Table 12. Offset 64 Data Format
Temperature -64C -63C -1C 0C 1C 10C 25C 50C 75C 100C 125C 191C Digital Output (10-Bit) (Note 1) 0000 0000 00 (diode fault) 0000 0001 00 0011 1111 00 0100 0000 00 0100 0001 00 0100 1010 00 0101 1001 00 0111 0010 00 1000 1001 00 1010 0100 00 1011 1101 00 1111 1111 00
Figure 26. Measuring Temperature Using a PNP Transistor
To prevent ground noise from interfering with the measurement, the more negative terminal of the sensor is not referenced to ground, but is biased above ground by an internal diode at the D- input. C1 can optionally be added as a noise filter (recommended maximum value of 1000 pF). However, a better option in noisy environments is to add a filter, as described in the section.
Remote Temperature Measurement
1. Bold numbers denote 2 LSBs of measurement in the Extended Resolution 2 register (Register 0x77) with 0.25C resolution.
Thermal Diode Temperature Measurement Method
A simple method of measuring temperature is to exploit the negative temperature coefficient of a diode, measuring the base-emitter voltage (VBE) of a transistor operated at constant current. Unfortunately, this technique requires calibration to null out the effect of the absolute value of VBE, which varies from device to device. The technique used in the ADT7490 is to measure the change in VBE when the device is operated at three different currents. Previous devices have used only two operating currents, but the use of a third current allows automatic cancellation of resistances in series with the external temperature sensor. Figure 28 shows the input signal conditioning used to measure the output of an external temperature sensor. This figure shows the external sensor as a substrate transistor, but it could equally be a discrete transistor, such as a 2N3904/2N3906.
The ADT7490 can measure the temperature of two remote diode sensors or diode-connected transistors connected to Pin 10 and Pin 11, or Pin 12 and Pin 13. The forward voltage of a diode or diode-connected transistor operated at a constant current exhibits a negative temperature coefficient of about -2 mV/C. Unfortunately, the absolute value of VBE varies from device to device, and individual calibration is required to null this out. Therefore, the technique is unsuitable for mass production. The technique used in the ADT7490 is to measure the change in VBE when the device is operated at three different currents. This is given by:
DV BE + KT q In(N)
(eq. 2)
where: k is the Boltzmann constant. q is the charge on the carrier. T is the absolute temperature in Kelvin. N is the ratio of the two currents. To measure DVBE, the operating current through the sensor is switched among three related currents. N1 x I and N2 x I are different multiples of the current I, as shown in Figure 27. The currents through the temperature diode are
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switched between I and N1 x I, giving DVBE1, and then between I and N2 x I, giving DVBE2. The temperature can then be calculated using the two DVBE measurements. This method can also cancel the effect of any series resistance on the temperature measurement. The resulting DVBE waveforms are passed through a 65 kHz low-pass filter to remove noise and then to a chopper-stabilized amplifier. This amplifies and rectifies the waveform to produce a dc voltage proportional to DVBE. The ADC digitizes this voltage, and a temperature
VDD I N2 y I N1 y I IBIAS
measurement is produced. To reduce the effects of noise, digital filtering is performed by averaging the results of 16 measurement cycles. The results of remote temperature measurements are stored in 10-bit, twos complement format, as listed in Table 11. The extra resolution for the temperature measurements is held in the Extended Resolution Register 2 (0x77). This gives temperature readings with a resolution of 0.25C.
REMOTE SENSING TRANSISTOR D+ D-
LPF
VOUT+ TO ADC
fC = 65kHz
VOUT-
Figure 27. Signal Conditioning for Remote Diode Temperature Sensors Series Resistance Cancellation
Parasitic resistance to the ADT7490 D+ and D- inputs (seen in series with the remote diode) is caused by a variety of factors, including PCB track resistance and track length. This series resistance appears as a temperature offset in the remote sensor's temperature measurement. This error typically causes a 0.5C offset per ohm of parasitic resistance in series with the remote diode. The ADT7490 automatically cancels out the effect of this series resistance on the temperature reading, giving a more accurate result without the need for user characterization of this resistance. The ADT7490 is designed to automatically cancel, typically up to 1.5 kW of resistance. By using an advanced temperature measurement method, this is transparent to the user. This feature allows resistances to be added to the sensor path to produce a filter, allowing the part to be used in noisy environments.
Noise Filtering
The construction of a filter allows the ADT7490 and the remote temperature sensor to operate in noisy environments. Figure 28 shows a low-pass RC filter with the following values:
R + 100 W, C + 1 nF
(eq. 3)
This filtering reduces both common-mode noise and differential noise.
100 REMOTE TEMPERATURE SENSOR 1nF 100 D- D+
Figure 28. Filter Between Remote Sensor and ADT7490
Factors Affecting Diode Accuracy
Remote Sensing Diode
For temperature sensors operating in noisy environments, previous practice was to place a capacitor across the D+ pin and the D- pin to help combat the effects of noise. However, large capacitance affect the accuracy of the temperature measurement, leading to a recommended maximum capacitor value of 1000 pF. This capacitor reduces the noise, but does not eliminate it, which makes using the sensor difficult in a very noisy environment. The ADT7490 has a major advantage over other devices for eliminating the effects of noise on the external sensor. Using the series resistance cancellation feature, a filter can be constructed between the external temperature sensor and the part. The effect of any filter resistance seen in series with the remote sensor is automatically canceled from the temperature result.
The ADT7490 is designed to work with either substrate transistors built into processors or discrete transistors. Substrate transistors are generally PNP types with the collector connected to the substrate. Discrete types can be either PNP or NPN transistors connected as a diode (base-shorted to the collector). To reduce the error due to variations in both substrate and discrete transistors, a number of factors should be taken into consideration: * The ideality factor, nf, of the transistor is a measure of the deviation of the thermal diode from ideal behavior. The ADT7490 is trimmed for an nf value of 1.008. Use the following equation to calculate the error introduced at a temperature T (C) when using a transistor whose nf does not equal 1.008. Refer to the data sheet for the related CPU to obtain the nf values.
DT + (nf * 1.008) 1.008 273.15 K ) T
(eq. 4)
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To factor this in, the user can write the DT value to the offset register. The ADT7490 automatically adds it to or subtracts it from the temperature measurement. * Some CPU manufacturers specify the high and low current levels of the substrate transistors. The high current level of the ADT7490, IHIGH, is 192 mA and the low level current, ILOW, is 12 mA. If the ADT7490 current levels do not match the current levels specified by the CPU manufacturer, it may be necessary to remove an offset. The CPU's data sheet advises whether this offset needs to be removed and how to calculate it. This offset can be programmed to the offset register. It is important to note that if more than one offset must be considered, the algebraic sum of these offsets must be programmed to the offset register. If a discrete transistor is used with the ADT7490, the best accuracy is obtained by choosing devices according to the following criteria: * Base-emitter voltage greater than 0.25 V at 12 mA at the highest operating temperature. * Base-emitter voltage less than 0.95 V at 192 mA at the lowest operating temperature. * Base resistance less than 100 W. * Small variation in hFE (such as 50 to 150) that indicates tight control of VBE characteristics. Transistors, such as 2N3904, 2N3906, or equivalents in SOT-23 packages, are suitable devices to use.
Reading Temperature from the ADT7490
The ADT7490 has temperature offset registers at Address 0x70, Address 0x71, and Address 0x72 for the Remote 1, local, and Remote 2 temperature channels, respectively. By performing a one-time calibration of the system, the user can determine the offset caused by system board noise and null it out using the offset registers. The offset registers automatically add a twos complement 8-bit reading to every temperature measurement. The temperature offset range and resolution is selected by setting Bit 1 of Register 0x7C. This ensures that the readings in the temperature measurement registers are as accurate as possible. Setting this bit to 0 means the LSBs add 0.5C offset to the temperature reading, so the 8-bit register effectively allows temperature offsets from -63C to +64C with a resolution of 0.5C. Setting this bit to 1 means the LSBs add 1C offset to the temperature reading, so the 8-bit register effectively allows temperature offsets of up to -63C to +127C with a resolution of 1C. For the PECI offset registers, the resolution is always 1C.
Temperature Offset Registers
Register 0x70, Remote 1 Temperature Offset = 0x00 (0C default) Register 0x71, Local Temperature Offset = 0x00 (0C default) Register 0x72, Remote 2 Temperature Offset = 0x00 (0C default) Register 0x94, PECI0 Temperature Offset = 0x00 (0C default) Register 0x95, PECI1 Temperature Offset = 0x00 (0C default) Register 0x96, PECI2 Temperature Offset = 0x00 (0C default) Register 0x97, PECI3 Temperature Offset = 0x00 (0C default)
Temperature Measurement Limit Registers
It is important to note that temperature can be read from the ADT7490 as an 8-bit value (with 1C resolution) or as a 10-bit value (with 0.25C resolution). If only 1C resolution is required, the temperature readings can be read back at any time and in no particular order. If the 10-bit measurement is required, it involves a 2-register read for each measurement. The Extended Resolution 2 register (0x77) should be read first. This causes all temperature reading registers to be frozen until all temperature reading registers have been read from. This prevents an MSB reading from being updated while its two LSBs are being read and vice versa.
Nulling Out Temperature Errors
Associated with each temperature measurement channel are high and low limit registers. Exceeding the programmed high or low limit causes the appropriate status bit to be set. Exceeding either limit can also generate SMBALERT interrupts (depending on the way the interrupt mask register is programmed and assuming that SMBALERT is set as an output on the appropriate pin).
Additional ADC Functions for Temperature Measurement
A number of other functions are available on the ADT7490 to offer the system designer increased flexibility.
Turn-Off Averaging
As CPUs run faster, it becomes more difficult to avoid high frequency clocks when routing the D+/D- traces around a system board. Even when recommended layout guidelines are followed, some temperature errors may still be attributable to noise coupled onto the D+/D- lines. Constant high frequency noise usually attenuates or increases temperature measurements by a linear, constant value.
For each temperature measurement read from a value register, 16 readings have actually been made internally, and the results averaged, before being placed into the value register. Sometimes it is necessary to take a very fast measurement. Setting Bit 4 of Configuration Register 2 (0x73) turns averaging off. The default round-robin cycle time with averaging off is a maximum of 23 ms.
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Table 13. Conversion Time with Averaging Disabled
Channel Voltage Channels Remote Temperature 1 Remote Temperature 2 Local Temperature Measurement Time (ms) 0.7 7 7 1.3
FANS 100% TEMPERATURE
THERM LIMIT
HYSTERESIS (5C)
When Bit 7 of Configuration Register 6 (0x10) is set, the default round-robin cycle time increases to a maximum of 193 ms.
Table 14. Conversion Time with Averaging Enabled
Channel Voltage Channels Remote Temperature Local Temperature Measurement Time (ms) 11 39 12
Figure 29. THERM Temperature Limit Operation
THERM can be disabled by setting Bit 2 of Configuration Register 4 (0x7D). THERM can also be disabled by: * In Offset 64 mode, writing -64C to the appropriate THERM temperature limit. * In twos complement mode, writing -128C to the appropriate THERM temperature limit. Limits, Status Registers, and Interrupts
Limit Values
Single-Channel ADC Conversions
Setting Bit 6 of Configuration Register 2 (Register 0x73) places the ADT7490 into single-channel ADC conversion mode. In this mode, the ADT7490 can be made to read a single temperature channel only. The appropriate ADC channel is selected by writing to Bits [7:4] of the TACH1 Minimum High Byte register (0x55).
Table 15. Programming Single-Channel ADC Mode for Temperatures
Bits [7:4], Register 0x55 Remote 1 Temperature Local Temperature Remote 2 Temperature Channel Selected 0101 0110 0111
Associated with each measurement channel on the ADT7490 are high and low limits. These can form the basis of system status monitoring; a status bit can be set for any out-of-limit condition and is detected by polling the device. Alternatively, SMBALERT interrupts can be generated to flag out-of-limit conditions to a processor or micro-controller.
8-Bit Limits
The following is a list of 8-bit limits on the ADT7490:
Voltage Limit Registers
Register 0x44, +2.5 VIN Low Limit = 0x00 default Register 0x45, +2.5 VIN High Limit = 0xFF default Register 0x46, VCCP Low Limit = 0x00 default Register 0x47, VCCP High Limit = 0xFF default Register 0x48, VCC Low Limit = 0x00 default Register 0x49, VCC High Limit = 0xFF default Register 0x4A, +5 VIN Low Limit = 0x00 default Register 0x4B, +5 VIN High Limit = 0xFF default Register 0x4C, +12 VIN Low Limit = 0x00 default Register 0x4D, +12 VIN High Limit = 0xFF default Register 0x84, VTT Low Limit = 0x00 default Register 0x86, VTT High Limit = 0xFF default Register 0x85, IMON Low Limit = 0x00 default Register 0x87, IMON High = 0xFF default
Temperature Limit Registers
Configuration Register 2 (Register 0x73)
Bit 4 (AVG) = 1, averaging off. Bit 6 (CONV) = 1, single-channel convert mode.
Overtemperature Events
Overtemperature events on any of the temperature channels can be detected and dealt with automatically in automatic fan speed control mode. Register 0x6A to Register 0x6C are the THERM temperature limits for the local and remote diode temperature channels. The equivalent PECI limit is TCONTROL in Register 0x3D. When a temperature exceeds its THERM temperature limit, all PWM outputs run at 100% duty cycle (default). This can be changed to maximum PWM duty cycle as programmed in Register 0x38, Register 0x39, and Register 0x3A, by setting Bit 3 of Register 0x7D. The fans run at this speed until the temperature drops below THERM minus hysteresis. This can be disabled by setting the BOOST bit in Configuration Register 3, Bit 2 (0x78). The hysteresis value for the THERM temperature limit is the value programmed into the hysteresis registers (0x6D and 0x6E). The default hysteresis value is 4C.
Register 0x4E, Remote 1 Temperature Low Limit = 0x81 default Register 0x4F, Remote 1 Temperature High Limit = 0x7F default Register 0x6A, Remote 1 THERM Temperature Limit = 0x64 default Register 0x50, Local Temperature Low Limit = 0x81 default Register 0x51, Local Temperature High Limit = 0x7F default
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Register 0x6B, Local THERM Temperature Limit = 0x64 default Register 0x52, Remote 2 Temperature Low Limit = 0x81 default Register 0x53, Remote 2 Temperature High Limit = 0x7F default Register 0x6C, Remote 2 THERM Temperature Limit = 0x64 default Register 0x34, PECI Low Limit = 0x81 default Register 0x35, PECI High Limit = 0x00 default Register 0x3D, PECI TCONTROL Limit = 0x00 default
THERM Timer Limit Register
Register 0x7A, THERM Timer Limit = 0x00 default
16-Bit Limits
The fan TACH measurements are 16-bit results. The fan TACH limits are also 16 bits, consisting of a high byte and low byte. Only high limits exist for fan TACHs because fans running under speed or stalled are normally the only conditions of interest. Because the fan TACH period is actually being measured, exceeding the limit indicates a slow or stalled fan.
Fan Limit Registers
input can be read out at any time. For applications where the monitoring cycle time is important, it can easily be calculated. The total number of channels measured consists of * Six dedicated supply voltage inputs * Supply voltage (VCC pin) * Local temperature * Two remote temperatures As mentioned previously, the ADC performs round-robin conversions and takes 11 ms for each voltage measurement, 12 ms for a local temperature reading, and 39 ms for each remote temperature reading. The total monitoring cycle time for averaged voltage and temperature monitoring is, therefore, nominally
(7 11) ) 12 ) (2 39) + 167 ms
(eq. 5)
Fan TACH measurements and PECI thermal measurements are made in parallel and are not synchronized with the analog measurements in any way.
Interrupt Status Registers
Register 0x54, TACH1 Minimum Low Byte = 0xFF default Register 0x55, TACH1 Minimum High Byte = 0xFF default Register 0x56, TACH2 Minimum Low Byte = 0xFF default Register 0x57, TACH2 Minimum High Byte = 0xFF default Register 0x58, TACH3 Minimum Low Byte = 0xFF default Register 0x59, TACH3 Minimum High Byte = 0xFF default Register 0x5A, TACH4 Minimum Low Byte = 0xFF default Register 0x5B, TACH4 Minimum High Byte = 0xFF default
Out-of-Limit Comparisons
Once all limits have been programmed, the ADT7490 can be enabled for monitoring. The ADT7490 measures all voltage and temperature measurements in round-robin format and sets the appropriate status bit to indicate out-of-limit conditions. TACH measurements are not part of this round-robin cycle. Comparisons are done differently depending on whether the measured value is being compared to a high or low limit. High Limit > Comparison Performed Low Limit Comparison Performed Voltage and temperature channels use a window comparator for error detecting and, therefore, have high and low limits. Fan speed measurements use only a low limit.
Analog Monitoring Cycle Time
The analog monitoring cycle begins when a 1 is written to the start bit (Bit 0) of Configuration Register 1 (0x40). The ADC measures each analog input in turn and, as each measurement is completed, the result is automatically stored in the appropriate value register. This round-robin monitoring cycle continues unless disabled by writing a 0 to Bit 0 of Configuration Register 1. As the ADC is normally left to free-run in this manner, the time taken to monitor all the analog inputs is normally not of interest, because the most recently measured value of any
The results of limit comparisons are stored in Interrupt Status Register 1 to Interrupt Status Register 4. The status register bit for each channel reflects the status of the last measurement and limit comparison on that channel. If a measurement is within limits, the corresponding interrupt status register bit is cleared to 0. If the measurement is out of limit, the corresponding interrupt status register bit is set to 1. The state of the various measurement channels can be polled by reading the interrupt status registers over the serial bus. In Bit 7 (OOL) of Interrupt Status Register 1 (0x41), a Logic 1 indicates an out-of-limit event has been flagged in Interrupt Status Register 2. This means the user also needs to read Interrupt Status Register 2. There is a similar OOL bit in Interrupt Status Register 2 and Interrupt Status Register 3, indicating an out-of-limit event in the next status register. Alternatively, Pin 10 or Pin 14 can be configured as an SMBALERT output. This hard interrupt automatically notifies the system supervisor of an out-of-limit condition. Reading the interrupt status registers clears the appropriate status bit as long as the error condition that caused the interrupt has cleared. Interrupt status register bits are sticky. Whenever an interrupt status bit is set, indicating an out-of-limit condition, it remains set even if the event that caused it has gone away (until read). The only way to clear the interrupt status bit is to read the interrupt status register after the event has gone away. Interrupt status mask registers allow individual interrupt sources to be masked from causing an SMBALERT on the dedicated alert pin. However, if one of these masked interrupt sources goes out of limit, its associated interrupt status bit is set in the interrupt status registers. Full details of the Interrupt Status and Interrupt Mask registers associated with each measurement channels are detailed in the Table 16 and in the full register map in the Register Tables section.
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Table 16. Interrupt Status and Interrupt Mask Register Address and Bit Assignments
Interrupt Status Register 0x41 0x42 0x43 0x81 Interrupt Mask Register 0x74 0x75 0x82 0x83 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
OOL D2 FAULT OOL VTT
R2T D1 FAULT RES IMON
LT FAN4/THERM RES PECI3
R1T FAN3 RES PECI2
+5 VIN FAN2 OVT PECI1
VCC FAN1 COM M RES
VCCP OOL DATA RES
+2.5 VIN/THERM +12 VIN PECI0 RES
SMBALERT Interrupt Behavior
The ADT7490 can be polled for status, or an SMBALERT interrupt can be generated for out-of-limit conditions. It is important to note how the SMBALERT output and status bits behave when writing interrupt handler software.
HIGH LIMIT
corresponding interrupt mask bit to 0. This causes the SMBALERT output and status bits to behave as shown in Figure 31.
Masking Interrupt Sources
TEMPERATURE CLEARED ON READ (TEMP BELOW LIMIT)
STICKY STATUS BIT TEMP BACK IN LIMIT (STATUS BIT STAYS SET)
The interrupt mask registers allow individual interrupt sources to be masked out to prevent SMBALERT interrupts. Note that masking an interrupt source prevents only the SMBALERT output from being asserted; the appropriate status bit is set normally (see Figure 31). Full details of the status and mask registers associated with each measurement channel are detailed in Table 16 and Table 20.
HIGH LIMIT
SMBALERT
Figure 30. SMBALERT and Status Bit Behavior
TEMPERATURE
Figure 30 shows how the SMBALERT output and sticky status bits behave. Once a limit is exceeded, the corresponding status bit is set to 1. The status bit remains set until the error condition subsides and the status register is read. The status bits are referred to as sticky, because they remain set until read by software. This ensures that an out-of-limit event cannot be missed if software is polling the device periodically. Note that the SMBALERT output remains low for the entire duration that a reading is out of limit and until the status register has been read. This has implications on how software handles the interrupt.
Handling SMBALERT Interrupts
STICKY STATUS BIT
CLEARED ON READ (TEMP BELOW LIMIT)
TEMP BACK IN LIMIT (STATUS BIT STAYS SET) SMBALERT INTERRUPT MASK BIT SET
INTERRUPT MASK BIT CLEARED (SMBALERT REARMED)
Figure 31. How Masking the Interrupt Source Affects SMBALERT Output Enabling the SMBALERT Interrupt Output
To prevent the system from being tied up servicing interrupts, it is recommend to handle the SMBALERT interrupt as follows: 1. Detect the SMBALERT assertion. 2. Enter the interrupt handler. 3. Read the status registers to identify the interrupt source. 4. Mask the interrupt source by setting the appropriate mask bit in the interrupt mask registers (0x74, 0x75, 0x82, and 0x83). 5. Take the appropriate action for a given interrupt source. 6. Exit the interrupt handler. 7. Periodically poll the status registers. If the interrupt status bit has cleared, reset the
The SMBALERT interrupt function is disabled by default. Pin 10 or Pin 14 can be reconfigured as an SMBALERT output to signal out-of-limit conditions.
Table 17. Configuring Pin 10 as SMBALERT Output
Register Configuration Register 3 (Register 0x78), Bit 0 Bit Setting [1] Pin 10 = SMBALERT [0] Pin 10 = PWM2 (default)
Assigning THERM Functionality to a Pin
Pin 14 on the ADT7490 has three possible functions: SMBALERT, THERM, and TACH4. The user chooses the required functionality by setting Bit 0 and Bit 1 of Configuration Register 4 at Address 0x7D.
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If THERM is enabled (Bit 1, Configuration Register 3 at Address 0x78), * Pin 22 becomes THERM. * If Pin 14 is configured as THERM (Bit 0 and Bit 1 of Configuration Register 4 at Address 0x7D), THERM is enabled on this pin.
THERM Timer
* Pin 22 becomes a 2.5 VIN measurement input. * If Pin 14 is configured as THERM, THERM is disabled
on this pin.
Table 18. Configuring Pin 14 in Register 0x7D
Bit 1 0 0 1 1 Bit 0 0 1 0 1 Function TACH4 THERM SMBALERT Reserved
If THERM is not enabled,
THERM as an Input
The ADT7490 has an internal timer to measure THERM assertion time. For example, the THERM input can be connected to the PROCHOT output of a CPU to measure system performance. The THERM input can also be connected to the output of a trip point temperature sensor. The timer is started on the assertion of the ADT7490 THERM input and stopped when THERM is deasserted. The timer counts THERM times cumulatively, that is, the timer resumes counting on the next THERM assertion. The THERM timer continues to accumulate THERM assertion times until the timer is read (it is cleared on read), or until it reaches full scale. If the counter reaches full scale, it stops at that reading until cleared. The 8-bit THERM timer status register (0x79) is designed so that Bit 0 is set to 1 on the first THERM assertion. Once the cumulative THERM assertion time has exceeded 45.52 ms, Bit 1 of the THERM timer is set and Bit 0 now becomes the LSB of the timer with a resolution of 22.76 ms (see Figure 33).
THERM
When THERM is configured as an input, the user can time assertions on the THERM pin. This can be useful for connecting to the PROCHOT output of a CPU to gauge system performance. The user can also set up the ADT7490 so that the fans run at 100% when the THERM pin is driven low externally. The fans run at 100% for the duration of the time that the THERM pin is pulled low. This is done by setting the BOOST bit (Bit 2) in Configuration Register 3 (Address 0x78) to 1. This works only if the fan is already running, for example, in manual mode when the current duty cycle is above 0x00, or in automatic mode when the temperature is above TMIN. If the temperature is below TMIN or if the duty cycle in manual mode is set to 0x00, pulling the THERM low externally has no effect. See Figure 32 for more information.
THERM TIMER (REG. 0x79)
00000001 76543210
THERM ASSERTED 22.76ms
THERM
ACCUMULATE THERM LOW ASSERTION TIMES THERM TIMER (REG. 0x79) 00000010 76543210
THERM ASSERTED 45.52ms
THERM
ACCUMULATE THERM LOW ASSERTION TIMES TMIN THERM TIMER (REG. 0x79) 00000101 7 6 5 4 3 2 1 0 THERM ASSERTED 113.8ms (91.04ms + 22.76ms)
THERM
Figure 33. Understanding the THERM Timer
THERM ASSERTED TO LOW AS AN INPUT: FANS DO NOT GO TO 100%, BECAUSE TEMPERATURE IS BELOW TMIN. THERM ASSERTED TO LOW AS AN INPUT: FANS DO NOT GO TO 100%, BECAUSE TEMPERATURE IS ABOVE TMIN
When using the THERM timer, be aware of the following: After a THERM timer read (Register 0x79): * The contents of the timer are cleared on read. * Bit 5 of Interrupt Status 2 register (0x42) needs to be cleared (assuming that the THERM timer limit has been exceeded).
Figure 32. Asserting THERM Low as an Input in Automatic Fan Speed Control Mode
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If the THERM timer is read during a THERM assertion, the following happens: * The contents of the timer are cleared. * Bit 0 of the THERM timer is set to 1, because a THERM assertion is occurring. * The THERM timer increments from zero. * If the THERM timer limit (Register 0x7A) = 0x00, the F4P bit is set.
Generating SMBALERT Interrupts from THERM Timer Events
The ADT7490 can generate SMBALERTs when a programmable THERM timer limit has been exceeded. This allows the system designer to ignore brief, infrequent THERM assertions while capturing longer THERM timer events. Register 0x7A is the THERM timer limit register. This 8-bit register allows a limit from 0 sec (first THERM assertion) to 5.825 sec to be set before an SMBALERT is generated. The THERM timer value is compared with the contents of the THERM timer limit register. If the THERM timer value exceeds the THERM timer limit value, the FAN4 bit (Bit 5) of Status Register 2 is set and an SMBALERT is generated. Note that depending on which pins are configured as a THERM timer, setting the FAN4/THERM bit (Bit 5) of the Interrupt Mask Register 2 (0x75), or bit 0 of the Interrupt Mask Register 1 (0x74), masks out SMBALERT; although the FAN4 bit of Interrupt Status Register 2 is still set if the THERM timer limit is exceeded. Figure 34 is a functional block diagram of the THERM timer, THERM limit, and its associated circuitry. Writing a value of 0x00 to the THERM Timer Limit register (0x7A) causes an SMBALERT to be generated on the first THERM assertion. A THERM timer limit value of 0x01 generates an SMBALERT once cumulative THERM assertions exceed 45.52 ms.
Configuring the Relevant THERM Behavior
1. Configure the desired pin as the THERM timer input. Setting Bit 1 (THERM timer enable) of Configuration Register 3 (Register 0x78) enables the THERM timer monitoring functionality. This is
disabled on Pin 14 and Pin 22 by default. Setting Bit 0 and Bit 1 (Pin 14 Func) of Configuration Register 4 (Register 0x7D) enables THERM timer output functionality on Pin 22 (Bit 1 of Configuration Register 3, THERM, must also be set). Pin 14 can also be used as TACH4. 2. Select the desired fan behavior for THERM timer events. Assuming the fans are running, setting Bit 2 (BOOST bit) of Configuration Register 3 (Register 0x78) causes all fans to run at 100% duty cycle whenever THERM is asserted. This allows fail-safe system cooling. If this bit = 0, the fans run at their current settings and are not affected by THERM events. If the fans are not already running when THERM is asserted, the fans do not run to full speed. 3. Select whether THERM timer events should generate SMBALERT interrupts. Bit 5 of Interrupt Mask Register 2 (0x75) or Bit 0 of Interrupt Mask Register 1 (0x74), depending on which pins are configured as a THERM timer, when set, masks out SMBALERTs when the THERM timer limit value is exceeded. This bit should be cleared if SMBALERTs based on THERM events are required. 4. Select a suitable THERM limit value. This value determines whether an SMBALERT is generated on the first THERM assertion, or only if a cumulative THERM assertion time limit is exceeded. A value of 0x00 causes an SMBALERT to be generated on the first THERM assertion. 5. Select a THERM monitoring time. This value specifies how often OS- or BIOS-level software checks the THERM timer. For example, BIOS can read the THERM timer once an hour to determine the cumulative THERM assertion time. If, for example, the total THERM assertion time is <22.76 ms in Hour 1, >182.08 ms in Hour 2, and >2.914 sec in Hour 3, this indicates that system performance is degrading significantly because THERM is asserting more frequently on an hourly basis.
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2.914s 1.457s 728.32ms THERM TIMER LIMIT 364.16ms (REGISTER 0x7A) 182.08ms 91.04ms 45.52ms 22.76ms 2.914s 1.457s 728.32ms 364.16ms THERM TIMER STATUS 182.08ms (REGISTER 0x79) 91.04ms 45.52ms 22.76ms
01234567
76543210
THERM THERM TIMER CLEARED ON READ
COMPARATOR
IN
OUT LATCH RESET
FAN4 BIT (BIT 5) INTERRUPT STATUS 2 REGISTER
SMBALERT
CLEARED ON READ
1 = MASK FAN4 BIT (BIT 5) INTERRUPT MASK REGISTER 2 (REGISTER 0x75)
Figure 34. Functional Block Diagram of THERM Monitoring Circuitry
Alternatively, OS- or BIOS-level software can time-stamp when the system is powered on. If an SMBALERT is generated due to the THERM timer limit being exceeded, another time-stamp can be taken. The difference in time can be calculated for a fixed THERM timer limit time. For example, if it takes one week for a THERM timer limit of 2.914 sec to be exceeded, and the next time it takes only 1 hour, this is an indication of a serious degradation in system performance.
Configuring the THERM Pin as an Output
THERM output feature for the Remote 1, local, and Remote 2 temperature channels, respectively. Figure 35 shows how the THERM pin asserts low as an output in the event of a critical overtemperature.
THERM LIMIT 0.255C THERM LIMIT TEMP
In addition to monitoring THERM as an input, the ADT7490 can optionally drive THERM low as an output. When PROCHOT is bidirectional, THERM can be used to throttle the processor by asserting PROCHOT. The user can preprogram system-critical thermal limits. If the temperature exceeds a thermal limit by 0.25C, THERM asserts low. If the temperature is still above the thermal limit on the next monitoring cycle, THERM stays low. THERM remains asserted low until the temperature is equal to or below the thermal limit. Because the temperature for that channel is measured only once for every monitoring cycle, after THERM asserts, it is guaranteed to remain low for at least one monitoring cycle. The THERM pin can be configured to assert low if the Remote 1 THERM, local THERM, Remote 2 THERM or PECI temperature limits are exceeded by 0.25C. The THERM temperature limit registers are at Register 0x6A, Register 0x6B, and Register 0x6C, respectively. Setting Bits [5:7] of Configuration Register 5 (0x7C) enables the
THERM
MONITORING CYCLE
Figure 35. Asserting THERM as an Output, Based on Tripping THERM Limits
An alternative method of disabling THERM is to program the THERM temperature limit to -63C or less in Offset 64 mode, or -128C or less in twos complement mode; that is, for THERM temperature limit values less than -63C or -128C, respectively, THERM is disabled.
Enabling and Disabling THERM on Individual Channels.
The THERM pin can be enabled/disabled for individual or combinations of temperature channels using Bits [7:5] of Configuration Register 5 (0x7C).
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THERM Hysteresis
Setting Bit 0 of Configuration Register 7 (0x11) disables THERM hysteresis. If THERM hysteresis is enabled and THERM is disabled (Bit 2 of Configuration Register 4, 0x7D), the THERM event is not reflected in the status register and the fans do not go to full speed. If THERM hysteresis is disabled and THERM is disabled (Bit 2 of Configuration Register 4, 0x7D) and assuming the appropriate pin is configured as THERM, the THERM pin asserts low when a THERM event occurs. If THERM and THERM hysteresis are both enabled, the THERM output asserts as expected.
THERM Operation in Manual Mode
The MOSFET should also have a low on resistance to ensure that there is not a significant voltage drop across the FET, which would reduce the voltage applied across the fan and, therefore, the maximum operating speed of the fan. Figure 36 shows how to drive a 3-wire fan using PWM control.
12V 10kW TACH 10kW 4.7kW TACH 12V FAN 1N4148 12V
ADT7490
PWM
3.3V 10kW Q1 NDT3055L
In manual mode, THERM events do not cause fans to go to full speed, unless Bit 5 of Configuration Register 1 (0x40) is set to 1. Additionally, Bit 3 of Configuration Register 4 (0x7D) can be used to select PWM speed on THERM event (100% or maximum PWM). Bit 2 in Configuration Register 4 (0x7D) can be set to disable THERM events from affecting the fans.
Fan Drive Using PWM Control
Figure 36. Driving a 3-Wire Fan Using an N-Channel MOSFET
The ADT7490 uses pulse-width modulation (PWM) to control fan speed. This relies on varying the duty cycle (or on/off ratio) of a square wave applied to the fan to vary the fan speed. The external circuitry required to drive a fan using PWM control is extremely simple. For 4-wire fans, the PWM drive may need only a pullup resistor. In many cases, the 4-wire fan PWM input has a built-in, pullup resistor. The ADT7490 PWM frequency can be set to a selection of low frequencies or a single high PWM frequency. The low frequency options are used for 3-wire fans, while the high frequency option is usually used with 4-wire fans. For 3-wire fans, a single N-channel MOSFET is the only drive device required. The specifications of the MOSFET depend on the maximum current required by the fan being driven and the input capacitance of the FET. Because a 10 kW (or greater) resistor must be used as a PWM pullup, an FET with large input capacitance can cause the PWM output to become distorted and adversely affect the fan control range. This is a requirement only when using high frequency PWM mode. Typical notebook fans draw a nominal 170 mA, therefore, SOT devices can be used where board space is a concern. In desktops, fans typically draw 250 mA to 300 mA each. If several fans are driven in parallel from a single PWM output or drive larger server fans, the MOSFET must handle the higher current requirements. The only other stipulation is that the MOSFET should have a gate voltage drive, VGS < 3.3 V, for direct interfacing to the PWM output pin.
Figure 36 uses a 10 kW pullup resistor for the TACH signal. This assumes that the TACH signal is an open-collector from the fan. In all cases, the TACH signal from the fan must be kept below 3.6 V maximum to prevent damaging the ADT7490. Figure 37 shows a fan drive circuit using an NPN transistor such as a general-purpose MMBT2222. While these devices are inexpensive, they tend to have much lower current handling capabilities and higher on resistance than MOSFETs. When choosing a transistor, care should be taken to ensure that it meets the fan's current requirements. Ensure that the base resistor is chosen so that the transistor is saturated when the fan is powered on.
12V 10kW 10kW TACH 4.7kW TACH 12V FAN 1N4148 12V
ADT7490
3.3V 470W
PWM
Q1 MMBT2222
Figure 37. Driving a 3-Wire Fan Using an NPN Transistor
Because the fan drive circuitry in 4-wire fans is not switched on or off, as with previous PWM driven/powered fans, the internal drive circuit is always on and uses the PWM input as a signal instead of a power supply. This enables the internal fan drive circuit to perform better than 3-wire fans, especially for high frequency applications. Figure 38 shows a typical drive circuit for 4-wire fans.
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ADT7490
12V 12V 12V, 4-WIRE FAN 10kW TACH 10kW 4.7kW 3.3V 2kW PWM TACH VCC TACH PWM TACH4 3.3V 3.3V +V +V 3.3V 10k TYPICAL
ADT7490
ADT7490
TACH3
10k TYPICAL TACH 3.3V 3.3V 5V OR 12V FAN
1N4148 TACH 5V OR 12V FAN
Figure 38. Driving a 4-Wire Fan Driving Two Fans from PWM3
PWM3
10k TYPICAL Q1 NDT3055L
The ADT7490 has four TACH inputs available for fan speed measurement, but only three PWM drive outputs. If a fourth fan is being used in the system, it should be driven from the PWM3 output in parallel with the third fan. Figure 39 shows how to drive two fans in parallel using low cost NPN transistors. Figure 40 shows the equivalent circuit using a MOSFET. Because the MOSFET can handle up to 3.5 A, it is simply a matter of connecting another fan directly in parallel with the first. Care should be taken in designing drive circuits with transistors and FETs to ensure the PWM outputs are not required to source current, and that they sink less than the 5 mA maximum current specified in the data sheet.
Driving up to Three Fans from PWM3
Figure 40. Interfacing Two Fans in Parallel to the PWM3 Output Using a Single N-Channel MOSFET Laying Out 3-Wire Fans
Figure 41 shows how to lay out a common circuit arrangement for 3-wire fans.
12V OR 5V R1 1N4148 3.3V OR 5V R2 R4 PWM R3 Q1 MMBT2222
TACH
TACH measurements for fans are synchronized to particular PWM channels; for example, TACH1 is synchronized to PWM1. TACH3 and TACH4 are both synchronized to PWM3, so PWM3 can drive two fans. Alternatively, PWM3 can be programmed to synchronize TACH2, TACH3, and TACH4 to the PWM3 output. This allows PWM3 to drive two or three fans. In this case, the drive circuitry looks the same, as shown in Figure 39 and Figure 40. The SYNC bit in Register 0x62 enables this function. Synchronization is not required in high frequency mode when used with 4-wire fans.
SYNC, Enhanced Acoustics Register 1 (Register 0x62)
Figure 41. Planning for 3-Wire Fans on a PCB TACH Inputs
Bit 4 (SYNC) = 1, synchronizes TACH2, TACH3, and TACH4 to PWM3.
12V 3.3V 3.3V TACH3 1kW PWM3 2.2kW 3.3V Q1 MMBT3904 10kW 1N4148 TACH4 3.3V
ADT7490
Pin 9, Pin 11, Pin 12, and Pin 14 (when configured as TACH inputs) are high impedance inputs intended for fan speed measurement. Signal conditioning in the ADT7490 accommodates the slow rise and fall times typical of fan tachometer outputs. The maximum input signal range is 0 V to 3.6 V, even though VCC is 3.3 V. In the event that these inputs are supplied from fan outputs that exceed 0 V to 3.6 V, either resistive attenuation of the fan signal or diode clamping must be included to keep inputs within an acceptable range. Figure 42 to Figure 45 show circuits for the most common fan TACH outputs. If the fan TACH output has a resistive pullup to VCC, it can be connected directly to the fan input, as shown in Figure 42.
VCC 12V
Q2 MMBT2222
10kW Q3 MMBT2222
PULLUP 4.7kW TYP TACH OUTPUT TACH
FAN SPEED COUNTER
ADT7490
Figure 39. Interfacing Two Fans in Parallel to the PWM3 Output Using Low Cost NPN Transistors
Figure 42. Fan with TACH Pullup to VCC
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ADT7490
If the fan output has a resistive pullup to 12 V, or other voltage greater than 3.6 V, the fan output can be clamped with a Zener diode, as shown in Figure 43. The Zener diode voltage should be chosen so that it is greater than VIH of the TACH input but less than 3.6 V, allowing for the voltage tolerance of the Zener. A value of between 3.0 V and 3.6 V is suitable.
12V VCC
PULLUP 4.7kW TYPICAL
TACH OUTPUT
TACH ZD1*
FAN SPEED COUNTER
The fan counter does not count the fan TACH output pulses directly because the fan speed could be less than 1000 RPM, and it takes several seconds to accumulate a reasonably large and accurate count. Instead, the period of the fan revolution is measured by gating an on-chip 90 kHz oscillator into the input of a 16-bit counter for N periods of the fan TACH output (see Figure 46), so the accumulated count is actually proportional to the fan tachometer period and inversely proportional to the fan speed. N, the number of pulses counted, is determined by the settings of the TACH pulses per revolution register (0x7B). This register contains two bits for each fan, allowing one, two (default), three, or four TACH pulses to be counted.
CLOCK
ADT7490
*CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8 y V CC
Figure 43. Fan with TACH Pullup to Voltage > 3.6 V, for Example, 12 V Clamped with Zener Diode
PWM
If the fan has a strong pullup (less than 1 kW) to 12 V or a totem-pole output, a series resistor can be added to limit the Zener current, as shown in Figure 44.
5V OR 12V FAN PULLUP TYP <1k WOR TOTEM POLE VCC
TACH
1 2 3 4
Figure 46. Fan Speed Measurement
R1 10k W TACH OUTPUT TACH ZD1 ZENER* FAN SPEED COUNTER
Fan Speed Measurement Registers
ADT7490
The fan tachometer registers are 16-bit values consisting of a 2-byte read from the ADT7490.
Register 0x28, TACH1 Low Byte = 0x00 default Register 0x29, TACH1 High Byte = 0x00 default Register 0x2A, TACH2 Low Byte = 0x00 default Register 0x2B, TACH2 High Byte = 0x00 default Register 0x2C, TACH3 Low Byte = 0x00 default Register 0x2D, TACH3 High Byte = 0x00 default Register 0x2E, TACH4 Low Byte = 0x00 default Register 0x2F, TACH4 High Byte = 0x00 default
Reading Fan Speed from the ADT7490
*CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8 y V CC
Figure 44. Fan with Strong TACH Pullup to >VCC or Totem-Pole Output, Clamped with Zener Diode and Resistor
Alternatively, a resistive attenuator can be used, as shown in Figure 45. R1 and R2 should be chosen such that
2.0 V t V PULLUP R2 R PULLUP ) R1 ) R2 t 3.6 V
(eq. 6)
The fan inputs have an input resistance of nominally 160 kW to ground, which should be taken into account when calculating resistor values. With a pullup voltage of 12 V and pullup resistor less than 1 kW, suitable values for R1 and R2 are 100 kW and 40 kW, respectively. This gives a high input voltage of 3.42 V.
12V VCC
<1k W
R1 100k W TACH OUTPUT
TACH R2 40k
FAN SPEED COUNTER
ADT7490
Figure 45. Fan with Strong TACH Pullup to >VCC or Totem-Pole Output, Attenuated with R1/R2
The measurement of fan speeds involves a 2-register read for each measurement. The low byte should be read first. This causes the high byte to be frozen until both high and low byte registers have been read, preventing erroneous TACH readings. The fan tachometer reading registers report back the number of 11.11 ms period clocks (90 kHz oscillator) gated to the fan speed counter, from the rising edge of the first fan TACH pulse to the rising edge of the third fan TACH pulse (assuming two pulses per revolution are being counted). Because the device is essentially measuring the fan TACH period, the higher the count value, the slower the fan is actually running. A 16-bit fan tachometer reading of 0xFFFF indicates that either the fan has stalled or is running very slowly (<100 RPM). High Limit > Comparison Performed
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ADT7490
Because the actual fan TACH period is being measured, falling below a fan TACH limit by 1 sets the appropriate status bit and can be used to generate an SMBALERT.
Fan TACH Limit Registers
plotting fan speed measurements at 100% speed with different pulses per revolution setting, the smoothest graph with the lowest ripple determines the correct pulses per revolution value.
TACH Pulses per Revolution Register
The fan TACH limit registers are 16-bit values consisting of two bytes.
Register 0x54, TACH1 Minimum Low Byte = 0xFF default Register 0x55, TACH1 Minimum High Byte = 0xFF default Register 0x56, TACH2 Minimum Low Byte = 0xFF default Register 0x57, TACH2 Minimum High Byte = 0xFF default Register 0x58, TACH3 Minimum Low Byte = 0xFF default Register 0x59, TACH3 Minimum High Byte = 0xFF default Register 0x5A, TACH4 Minimum Low Byte = 0xFF default Register 0x5B, TACH4 Minimum High Byte = 0xFF default
Fan Speed Measurement Rate
Bits [1:0], FAN1 default = 2 pulses per revolution Bits [3:2], FAN2 default = 2 pulses per revolution Bits [5:4], FAN3 default = 2 pulses per revolution Bits [7:6], FAN4 default = 2 pulses per revolution 00 = 1 pulse per revolution 01 = 2 pulses per revolution 10 = 3 pulses per revolution 11 = 4 pulses per revolution
Fan Spin-Up
The fan TACH readings are normally updated once every second. When set, the FAST bit (Bit 3) of Configuration Register 3 (0x78), updates the fan TACH readings every 250 ms.
DC Bits
If any of the fans are not being driven by a PWM channel but are powered directly from 5.0 V or 12 V, their associated dc bit in Configuration Register 3 should be set. This allows TACH readings to be taken on a continuous basis for fans connected directly to a dc source. For 4-wire fans, once high frequency mode is enabled, the dc bits do not need to be set because this is automatically done internally.
Calculating Fan Speed
The ADT7490 has a unique fan spin-up function. It spins the fan at 100% PWM duty cycle until two TACH pulses are detected on the TACH input. When two TACH pulses have been detected, the PWM duty cycle goes to the expected running value, for example, 33%. The advantage of this is that fans have different spin-up characteristics and take different times to overcome inertia. The ADT7490 runs the fans just fast enough to overcome inertia and is quieter on spin-up than fans programmed to spin up for a given spin-up time.
Fan Startup Timeout
Assuming a fan with a two pulses per revolution, and with the ADT7490 programmed to measure two pulses per revolution, fan speed is calculated by Fan Speed (RPM) = (90,000 x 60)/Fan TACH Reading where Fan TACH Reading is the 16-bit fan tachometer reading.
Example
To prevent the generation of false interrupts as a fan spins up, because the fan is below running speed, the ADT7490 includes a fan startup timeout function. During this time, the ADT7490 looks for two TACH pulses. If two TACH pulses are not detected, an interrupt is generated. Fan startup timeout can be disabled by setting Bit 3 (FSPDIS) of Configuration Register 7 (0x11).
PWM1, PWM2, PWM3 Configuration (Register 0x5C, Register 0x5D, Register 0x5E)
TACH1 High Byte (Register 0x29) = 0x17 TACH1 Low Byte (Register 0x28) = 0xFF What is Fan 1 speed in RPM? Fan 1 TACH Reading = 0x17FF = 6143 (decimal) RPM = (f x 60)/Fan 1 TACH Reading RPM = (90000 x 60)/6143 Fan Speed = 879 RPM
Fan Pulses per Revolution
Bits [2:0] SPIN, startup timeout for PWM1 = 0x5C, PWM2 = 0x5D, and PWM3 = 0x5E. 000 = No startup timeout 001 = 100 ms 010 = 250 ms default 011 = 400 ms 100 = 667 ms 101 = 1 sec 110 = 2 sec 111 = 4 sec
Disabling Fan Startup Timeout
Different fan models can output either one, two, three, or four TACH pulses per revolution. Once the number of fan TACH pulses has been determined, it can be programmed into the TACH pulses per revolution register (0x7B) for each fan. Alternatively, this register can be used to determine the number or pulses per revolution output by a given fan. By
Although a fan startup makes fan spin-ups much quieter than fixed-time spin-ups, the option exists to use fixed spin-up times. Setting Bit 3 (FSPDIS) to 1 in Configuration Register 7 (Register 0x11) disables the spin-up for two TACH pulses. Instead, the fan spins up for the fixed time as selected in Register 0x5C to Register 0x5E.
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ADT7490
PWM Logic State
The PWM outputs can be programmed high for 100% duty cycle (non-inverted) or low for 100% duty cycle (inverted).
PWM1 Configuration (Register 0x5C)
Bits [7:5] of Register 0x5C to Register 0x5E (PWM Configuration) control the behavior of each PWM output.
PWM Configuration Registers (Register 0x5C to Register 0x5E)
Bit 4 (INV) 0 = Logic high for 100% PWM duty cycle (non-inverted) 1 = Logic low for 100% PWM duty cycle (inverted)
PWM2 Configuration (Register 0x5D)
Bits [7:5] (BHVR) 111 = manual mode Once under manual control, each PWM output can be manually updated by writing to Register 0x30 to Register 0x32 (PWMx current duty cycle registers).
Programming the PWM Current Duty Cycle Registers
Bit 4 (INV) 0 = Logic high for 100% PWM duty cycle 1 = Logic low for 100% PWM duty cycle
PWM3 Configuration (Register 0x5E)
Bit 4 (INV) 0 = Logic high for 100% PWM duty cycle (non-inverted) 1 = Logic low for 100% PWM duty cycle (inverted).
Low Frequency Mode PWM Drive Frequency
The PWM current duty cycle registers are 8-bit registers that allow the PWM duty cycle for each output to be set anywhere from 0% to 100% in steps of 0.39%. The value to be programmed into the PWMMIN register is given by Value (decimal) = PWMMIN/0.39%
Example 1
The PWM drive frequency can be adjusted for the application. Register 0x5F to Register 0x61 configure the PWM frequency for PWM1 to PWM3, respectively.
PWM1, PWM 2, PWM3 Frequency Registers (Register 0x5F to Register 0x61)
For a PWM duty cycle of 50%, Value (decimal) = 50%/0.39% = 128 (decimal) Value = 128 (decimal) or 0x80 (hexadecimal)
Example 2
For a PWM duty cycle of 33%, Value (decimal) = 33%/0.39% = 85 (decimal) Value = 85 (decimal) or 0x54 (hexadecimal)
PWM Duty Cycle Registers Register 0x30, PWM1 Current Duty Cycle = 0xFF (100% default) Register 0x31, PWM2 Current Duty Cycle = 0xFF (100% default) Register 0x32, PWM3 Current Duty Cycle = 0xFF (100% default)
Bits [2:0] FREQ 000 = 11.0 Hz 001 = 14.7 Hz 010 = 22.1 Hz 011 = 29.4 Hz 100 = 35.3 Hz default 101 = 44.1 Hz 110 = 58.8 Hz 111 = 88.2 Hz
High Frequency Mode PWM Drive
By reading the PWMx current duty cycle registers, the user can keep track of the current duty cycle on each PWM output, even when the fans are running in automatic fan speed control mode or acoustic enhancement mode. TRANGE defines the distance between TMIN and 100% PWM. For the ADT7467, ADT7468, and ADT7473, TRANGE is effectively a slope. For the ADT7475, ADT7476, and ADT7490, TRANGE is no longer a slope but defines the temperature region where the PWM output linearly ramps from PWMMIN to 100% PWM.
PWM = 100% PWMMAX
Setting Bit 3 of Register 0x5F, Register 0x60, and Register 0x61 enables high frequency mode for Fan 1, Fan 2, and Fan 3, respectively. In high frequency mode, the PWM drive frequency is always 22.5 kHz. When high frequency mode is enabled, the dc bits are automatically asserted internally and do not need to be changed.
Fan Speed Control
Programming TRANGE
The ADT7490 controls fan speed using automatic and manual modes. In automatic fan speed control mode, fan speed is automatically varied with temperature and without CPU intervention, once initial parameters are set up. The advantage is that, if the system hangs, the user is guaranteed that the system is protected from overheating. In manual fan speed control mode, the ADT7490 allows the duty cycle of any PWM output to be manually adjusted. This can be useful if the user wants to change fan speed in software or adjust PWM duty cycle output for test purposes.
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PWMMIN TRANGE PWM = 0% TMIN
Figure 47. TRANGE
ADT7490
Programming the Automatic Fan Speed Control Loop
To more efficiently understand the automatic fan speed control loop, using the ADT7490 evaluation board and software while reading this section is recommended. This section provides the system designer with an understanding of the automatic fan control loop, and provides step-by-step guidance on effectively evaluating and selecting critical system parameters. To optimize the system characteristics, the designer needs to give some thought to system configuration, including the number of fans, where they are located, and what temperatures are being measured in the particular system. The mechanical or thermal engineer who is tasked with the system thermal characterization should also be involved at the beginning of the system development process.
Manual Fan Control Overview
In unusual circumstances, it can be necessary to manually control the speed of the fans. Because the ADT7490 has an SMBus interface, a system can read back all necessary voltage, fan speed, and temperature information, and use this information to control the speed of the fans by writing to the current PWM duty cycle register (0x30, 0x31, and 0x32) of the appropriate fan. Bits [7:5] of the PWMx configuration registers (0x5C, 0x5D, and 0x5E) are used to set fans up for manual control.
THERM Operation in Manual Mode
In manual mode, if the temperature increases above the programmed THERM temperature limit, the fans automatically speed up to maximum PWM or 100% PWM, whichever way the appropriate fan channel is configured.
Automatic Fan Control Overview
The ADT7490 can automatically control the speed of fans based on the measured temperature. This is done independently of CPU intervention once the initial parameters are set up.
The ADT7490 has a local temperature sensor and two remote temperature channels that can be connected to a CPU on-chip thermal diode (available on Intel Pentium(R) class and other CPUs). These three temperature channels can be used as the basis for automatic fan speed control to drive fans using pulse-width modulation (PWM). Automatic fan speed control reduces acoustic noise by optimizing fan speed according to accurately measured temperature. Reducing fan speed can also decrease system current consumption. The automatic fan speed control mode is very flexible due to the number of programmable parameters, including TMIN and TRANGE. The TMIN and TRANGE values for a temperature channel and, therefore, for a given fan are critical, because they define the thermal characteristics of the system. The thermal validation of the system is one of the most important steps in the design process, so these values should be selected carefully. Figure 48 gives a top-level overview of the automatic fan control circuitry on the ADT7490. From a systems-level perspective, up to three system temperatures can be monitored and used to control three PWM outputs. The three PWM outputs can be used to control up to four fans. The ADT7490 allows the speed of four fans to be monitored. Each temperature channel has a thermal calibration block, allowing the designer to individually configure the thermal characteristics of each temperature channel. For example, users can decide to run the CPU fan when CPU temperature increases above 60C and a chassis fan when the local temperature increases above 45C. At this stage, the designer has not assigned these thermal calibration settings to a particular fan drive (PWM) channel. The right side of Figure 48 shows controls that are fan-specific. The designer has individual control over parameters such as minimum PWM duty cycle, fan speed failure thresholds, and even ramp control of the PWM outputs. Automatic fan control ultimately allows graceful fan speed changes that are less perceptible to the system user.
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ADT7490
THERMAL CALIBRATION 100% PWM MIN
PWM CONFIG PWM GENERATOR RAMP CONTROL (ACOUSTIC ENHANCEMENT) PWM1
TMIN REMOTE 1 = AMBIENT TEMP
TRANGE
0%
TACHOMETER 1 MEASUREMENT
TACH1 CPU FAN SINK
THERMAL CALIBRATION
100%
MUX
0%
PWM MIN
PWM CONFIG PWM GENERATOR
TMIN LOCAL = VRM TEMP
TRANGE
THERMAL CALIBRATION
RAMP CONTROL (ACOUSTIC ENHANCEMENT)
PWM2
100%
TACHOMETER 2 MEASUREMENT
TACH2
TMIN REMOTE 2 = GPU TEMP
TRANGE
0%
PWM MIN
FRONT CHASSIS PWM CONFIG PWM GENERATOR
THERMAL CALIBRATION
100%
RAMP CONTROL (ACOUSTIC ENHANCEMENT)
PWM3
TACHOMETER 3 AND 4 MEASUREMENT TMIN PECI = CPU TEMP TRANGE 0%
TACH3
REAR CHASSIS
Figure 48. Automatic Fan Control Block Diagram
Step 1: Hardware Configuration
During system design, the motherboard sensing and control capabilities should be addressed early in the design stages. Decisions about how these capabilities are used should involve the system thermal/mechanical engineer. Ask the following questions: * What ADT7490 functionality is used? * PWM2 or SMBALERT? * TACH4 fan speed measurement or overtemperature THERM function? * 2.5 VIN voltage monitoring or overtemperature THERM function? The ADT7490 offers multifunctional pins that can be reconfigured to suit different system requirements and physical layouts. These multifunction pins are software programmable. * How many fans are supported in the system, three or four? This influences the choice of whether to use the TACH4 pin or to reconfigure it for the THERM function. * Is the CPU fan to be controlled using the ADT7490, or will the CPU fan run at full speed 100% of the time? If run at 100%, it frees up a PWM output, but the system is louder.
* Where is the ADT7490 going to be physically located
in the system? This influences the assignment of the temperature measurement channels to particular system thermal zones. For example, locating the ADT7490 close to the VRM controller circuitry allows the VRM temperature to be monitored using the local temperature channel. After the system hardware configuration is determined, the fans can be assigned to particular temperature channels. Not only can fans be assigned to individual channels, but the behavior of the fans is also configurable. For example, fans can be run under automatic fan control, can be run manually (under software control), or can be run at the fastest speed calculated by multiple temperature channels. The mux is the bridge between temperature measurement channels and the three PWM outputs. Bits [7:5] (BHVR) of Register 0x5C, Register 0x5D, and Register 0x5E (PWM configuration registers) control the behavior of the fans connected to the PWM1, PWM2, and PWM3 outputs, respectively. The values selected for these bits determine how the multiplexer connects a temperature measurement channel to a PWM output.
Step 2: Configuring the Muxtiplexer
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ADT7490
Automatic Fan Control Multiplexer Options
Bits [7:5] (BHVR), Register 0x5C, Register 0x5D, and Register 0x5E, with the ALT bit (Bit 3) cleared to 0. 000 = Remote 1 temperature controls PWMx 001 = Local temperature controls PWMx 010 = Remote 2 temperature controls PWMx 101 = Fastest speed calculated by local and Remote 2 temperature controls PWMx 110 = Fastest speed calculated by all three temperature channels controls PWMx The fastest speed calculated options pertain to controlling one PWM output based on multiple temperature channels. The thermal characteristics of the three temperature zones can be set to drive a single fan. An example is the fan turning on when the Remote 1 temperature exceeds 60C or if the local temperature exceeds 45C. Setting the ALT bit in Register 0x5C, Register 0x5D, and Register 0x5E gives alternative behavior settings for Bits [7:5] of the PWM configuration registers. Bits [7:5] (BHVR), Register 0x5C, Register 0x5D, and Register 0x5E, with the ALT bit (Bit 3) set to 1. 000 = PECI0 reading controls PWMx 001 = PECI1 reading controls PWMx 010 = PECI2 reading controls PWMx 011 = PECI3 reading controls PWMx 101 = Fastest speed calculated by all four PECI readings controls PWMx 111 = Fastest speed calculated by all thermal zones (Local, Rem1, Rem2 and PECI) controls PWMx
Other Mux Options
TMIN is the temperature at which the fans start to turn on under automatic fan control. The speed at which the fan runs at TMIN is programmed later. The TMIN values chosen are temperature channel specific, for example, 25C for ambient channel, 30C for VRM temperature, and 40C for processor temperature. TMIN is an 8-bit value, either twos complement or Offset 64, that can be programmed in 1C increments. A TMIN register is associated with each temperature measurement channel: Remote 1, local, Remote 2 and PECI temperature. When the TMIN value is exceeded, the fan turns on and runs at the minimum PWM duty cycle. The fan turns off once the temperature has dropped below TMIN - THYST. To overcome fan inertia, the fan is spun up until two valid TACH rising edges are counted. See the Fan Startup Timeout section for more details. In some cases, primarily for psycho-acoustic reasons, it is desirable that the fan never switch off below TMIN. When set, Bits [7:5] of Enhanced Acoustics Register 1 (0x62) keep the fans running at the PWM minimum duty cycle if the temperature should fall below TMIN.
TMIN Registers Register 0x67, Remote 1 Temperature TMIN = 0x5A (90C default) Register 0x68, Local Temperature TMIN = 0x5A (90C default) Register 0x69, Remote 2 Temperature TMIN = 0x5A (90C default) Register 0x3B, PECI TMIN = 0xE0 (-32C default) Enhanced Acoustics Register 1 (Register 0x62)
Step 3: TMIN Settings for Thermal Calibration Channels
Bits [7:5] (BHVR), Register 0x5C, Register 0x5D, and Register 0x5E, with the ALT bit (Bit 3) cleared to 0. 011 = PWMx runs full speed 100 = PWMx disabled (default) 111 = Manual mode. PWMx is running under software control. In this mode, PWM duty cycle registers (Register 0x30 to Register 0x32) are writable and control the PWM outputs. Bits [7:5] (BHVR), Register 0x5C, Register 0x5D, and Register 0x5E, with the ALT bit (Bit 3) set to 1. 100 = PWMx runs at 100% duty cycle 110 = PWMx runs at 100% duty cycle
Bit 7 (MIN3) = 0, PWM3 is off (0% PWM duty cycle) when the temperature is below TMIN - THYST. Bit 7 (MIN3) = 1, PWM3 runs at PWM3 minimum duty cycle below TMIN - THYST. Bit 6 (MIN2) = 0, PWM2 is off (0% PWM duty cycle) when the temperature is below TMIN - THYST. Bit 6 (MIN2) = 1, PWM2 runs at PWM2 minimum duty cycle below TMIN - THYST. Bit 5 (MIN1) = 0, PWM1 is off (0% PWM duty cycle) when the temperature is below TMIN - THYST. Bit 5 (MIN1) = 1, PWM1 runs at PWM1 minimum duty cycle below TMIN - THYST.
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ADT7490
100% PWM DUTYCYCLE 0% TMIN
THERMAL CALIBRATION
100%
PWM MIN
PWM CONFIG PWM GENERATOR RAMP CONTROL (ACOUSTIC ENHANCEMENT) PWM1
TMIN REMOTE 2 = CPU TEMP
TRANGE
0% PWM MIN
TACHOMETER 1 MEASUREMENT PWM CONFIG PWM GENERATOR
TACH1 CPU FAN SINK RAMP CONTROL (ACOUSTIC ENHANCEMENT)
THERMAL CALIBRATION
100%
MUX
0% PWM MIN
PWM2
TMIN LOCAL = VRM TEMP
TRANGE
TACHOMETER 2 MEASUREMENT PWM CONFIG PWM GENERATOR
TACH2
THERMAL CALIBRATION
100%
RAMP CONTROL (ACOUSTIC ENHANCEMENT)
FRONT CHASSIS PWM3
TMIN REMOTE 1 = AMBIENT TEMP
TRANGE
0%
TACHOMETER 3 AND 4 MEASUREMENT
TACH3
Figure 49. Understanding the TMIN Parameter Step 4: PWMMIN for Each PWM (Fan) Output
REAR CHASSIS
PWMMIN is the minimum PWM duty cycle at which each fan in the system runs. It is also the start speed for each fan under automatic fan control once the temperature rises above TMIN. For maximum system acoustic benefit, PWMMIN should be as low as possible. Depending on the fan used, the PWMMIN setting is usually in the 20% to 33% duty cycle range. This value can be found through fan validation.
100% PWM DUTY CYCLE
More than one PWM output can be controlled from a single temperature measurement channel. For example, Remote 1 temperature can control PWM1 and PWM2 outputs. If two different fans are used on PWM1 and PWM2, the fan characteristics can be set up differently. As a result, Fan 1 driven by PWM1 can have a different PWMMIN value than that of Fan 2 connected to PWM2. Figure 51 illustrates this as PWM1MIN (front fan) turned on at a minimum duty cycle of 20%, while PWM2MIN (rear fan) is turned on at a minimum of 40% duty cycle. Note that both fans turn on at exactly the same temperature, defined by TMIN.
PWMMIN 0% TMIN TEMPERATURE
Figure 50. PWMMIN Determines Minimum PWM Duty Cycle
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ADT7490
100% PWM DUTY CYCLE
PWM2 PWM1
PWM2MIN PWM1MIN 0%
as low as possible, but should be capable of maintaining the processor temperature limit at an acceptable level. If the THERM temperature limit is exceeded, the fans are still boosted to 100% for fail-safe cooling. There is a PWMMAX limit for each fan channel. The default value of this register is 0xFF and has no effect unless it is programmed.
100% PWM DUTY CYCLE
TMIN
TEMPERATURE
PWMMAX
Figure 51. Operating Two Different Fans from a Single Temperature Channel Programming the PWMMIN Registers
PWMMIN 0% TMIN TEMPERATURE
The PWMMIN registers are 8-bit registers that allow the minimum PWM duty cycle for each output to be configured anywhere from 0% to 100%. This allows the minimum PWM duty cycle to be set in steps of 0.39%. The value to be programmed into the PWMMIN register is given by: Value (decimal) = PWMMIN/0.39%
Example 1
Figure 52. PWMMAX Determines Maximum PWM Duty Cycle Below the THERM Temperature Limit
For a minimum PWM duty cycle of 50%, Value (decimal) = 50%/0.39% = 128 (decimal) Value = 128 (decimal) or 0x80 (hexadecimal)
Example 2
The PWMMAX registers are 8-bit registers that allow the maximum PWM duty cycle for each output to be configured anywhere from 0% to 100%. This allows the maximum PWM duty cycle to be set in steps of 0.39%. The value to be programmed into the PWMMAX register is given by Value (decimal) = PWMMAX/0.39%
Example 1
Programming the PWMMAX Registers
For a minimum PWM duty cycle of 33%, Value (decimal) = 33%/0.39% = 85 (decimal) Value = 85 (decimal) or 0x54 (hexadecimal)
PWMMIN Registers Register 0x64, PWM1 Minimum Duty Cycle = 0x80 (50% default) Register 0x65, PWM2 Minimum Duty Cycle = 0x80 (50% default) Register 0x66, PWM3 Minimum Duty Cycle = 0x80 (50% default) Note on Fan Speed and PWM Duty Cycle
For a maximum PWM duty cycle of 50%, Value (decimal) - 50%/0.39% = 128 (decimal) Value = 128 (decimal) or 0x80 (hexadecimal)
Example 2
For a minimum PWM duty cycle of 75%, Value (decimal) = 75%/0.39% = 85 (decimal) Value = 192 (decimal) or 0xC0 (hexadecimal)
PWMMAX Registers Register 0x38, Maximum PWM1 Duty Cycle = 0xFF (100% default) Register 0x39, Maximum PWM2 Duty Cycle = 0xFF (100% default) Register 0x3A, Maximum PWM3 Duty Cycle = 0xFF (100% default)
The PWM duty cycle does not directly correlate to fan speed in RPM. Running a fan at 33% PWM duty cycle does not equate to running the fan at 33% speed. Driving a fan at 33% PWM duty cycle actually runs the fan at closer to 50% of its full speed. This is because fan speed in %RPM generally relates to the square root of PWM duty cycle. Given a PWM square wave as the drive signal, fan speed in RPM approximates to
% fanspeed + PWM Duty Cycle Step 5: PWMMAX for PWM (Fan) Outputs 10
(eq. 7)
PWMMAX is the maximum duty cycle that each fan in the system runs at under the automatic fan speed control loop. For maximum system acoustic benefit, PWMMAX should be
TRANGE is the range of temperature over which automatic fan control occurs once the programmed TMIN temperature has been exceeded. TRANGE is the temperature range between PWMMIN and 100% PWM where the fan speed changes linearly. Otherwise stated, it is the line drawn between the TMIN/PWMMIN and the (TMIN + TRANGE)/100% PWM intersection points.
Step 6: TRANGE for Temperature Channels
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TRANGE 100% PWM DUTY CYCLE 100% PWM DUTY CYCLE 10% 0% TMIN-HYST 305C 405C 455C 545C TMIN TEMPERATURE
PWMMIN 0%
Figure 53. TRANGE Parameter Affects Cooling Slope
The TRANGE is determined by the following procedure: 1. Determine the maximum operating temperature for that channel (for example, 70C). 2. Determine experimentally the fan speed (PWM duty cycle value) that does not exceed the temperature at the worst-case operating points. For example, 70C is reached when the fans are running at 50% PWM duty cycle. 3. Determine the slope of the required control loop to meet these requirements. 4. Using the ADT7490 evaluation software, graphically program and visualize this functionality. Ask a local Analog Devices representative for details. As PWMMIN is changed, the automatic fan control slope changes.
100% PWM DUTY CYCLE
TMIN
Figure 55. Increasing TRANGE Changes the AFC Slope
100% PWM DUTY CYCLE MAX PWM
10% 0% TRANGE TMIN-HYST
Figure 56. Changing PWM Max Does Not Change the AFC Slope
50% 33% 0% 305C TMIN
The TRANGE value can be selected for each temperature channel: Remote 1, local, Remote 2, and PECI temperature. Bits [7:4] (TRANGE) of Register 0x5F to Register 0x61 and Register 0x3C define the TRANGE value for each temperature channel.
Table 19. Selecting a TRANGE Value
Bits [7:4] (Note 1) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 TRANGE (5C) 2 2.5 3.33 4 5 6.67 8 10 13.33 16 20 26.67 32 (default) 40 53.33 80
Selecting TRANGE
Figure 54. Adjusting PWMMIN Changes the Automatic Fan Control Slope
As TRANGE is changed, the slope changes. As TRANGE gets smaller, the fans reach 100% speed with a smaller temperature change.
1. Register 0x5F configures Remote 1 TRANGE; Register 0x60 configures local TRANGE; Register 0x61 configures Remote 2 TRANGE, Register 0x3C configures PECI TRANGE.
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Actual Changes in PWM Output (Advanced Acoustics Settings)
While the automatic fan control algorithm describes the general response of the PWM output, it is also necessary to note that the enhanced acoustics registers (0x62, 0x63, and 0x3C) can be used to set/clamp the maximum rate of change of PWM output for a given temperature zone. This means that if TRANGE is programmed with an AFC slope that is quite steep, a relatively small change in temperature could cause a large change in PWM output and possibly an audible change in fan speed, which can be noticeable/annoying to end users. Decreasing the speed of the PWM output changes by programming the smoothing on the appropriate temperature channels (Register 0x62 and Register 0x63) changes how fast the fan speed increases/decreases in the event of a temperature spike. Slowly the PWM duty cycle increases until the PWM duty cycle reaches the appropriate duty cycle as defined by the AFC curve. Figure 57 shows PWM duty cycle vs. temperature for each TRANGE setting. Figure 57B shows how each TRANGE setting affects fan speed vs. temperature. As can be seen from the graph, the effect on fan speed is nonlinear.
100 90 80 PWM DUTY CYCLE (%) 70 60 50 40 30 20 10 0 0 20 40 60 80 TEMPERATURE ABOVE T MIN 100 120 25C 2.55C 3.335C 45C 55C
The graphs in Figure 57 assume the fan starts from 0% PWM duty cycle. Clearly, the minimum PWM duty cycle, PWMMIN, needs to be factored in to see how the loop actually performs in the system. Figure 58 shows how TRANGE is affected when the PWMMIN value is set to 20%. It can be seen that the fan actually runs at about 45% fan speed when the temperature exceeds TMIN.
100 90 80 PWM DUTY CYCLE (%) 70 60 50 40 30 20 10 0 0 20 40 60 80 TEMPERATURE ABOVE T MIN 100 120 25C 2.55C 3.335C 45C 55C 6.675C 85C 105C 13.35C 165C 205C 26.65C 325C 405C 53.35C 805C
(A)
100 90 80 FAN SPEED (% OF MAX) 70 60 50 40 30 20 10 0 0 20 40 60 80 TEMPERATURE ABOVE T MIN 100 120 25C 2.55C 3.335C 45C 55C 6.675C 85C 105C 13.35C 165C 205C 26.65C 325C 405C 53.35C 805C
6.675C 85C 105C 13.35C 165C 205C 26.65C 325C 405C 53.35C 805C
(A)
100 90 80 FAN SPEED (% OF MAX) 70 60 50 40 30 20 10 0 0 20 40 60 80 TEMPERATURE ABOVE T MIN 100 120 25C 2.55C 3.335C 45C 55C 6.675C 85C 105C 13.35C 165C 205C 26.65C 325C 405C 53.35C 805C
(B)
Figure 58. TRANGE and % Fan Speed Slopes with PWMMIN = 20%
(B)
Figure 57. TRANGE vs. Actual Fan Speed (Not PWM Drive) Profile
TTHERM is the absolute maximum temperature allowed on a temperature channel. For PECI temperature channels, the equivalent parameter is TCONTROL. Above this temperature, a component such as the CPU or VRM may be operating beyond its safe operating limit. When the temperature measured exceeds TTHERM, all fans are driven at 100% PWM duty cycle (full speed) to provide critical system cooling. The fans remain running at 100% until the temperature drops below TTHERM minus hysteresis, where hysteresis is the number programmed into the hysteresis registers (0x6D and 0x6E). The default hysteresis value is 4C. The TTHERM limit should be considered the maximum worst-case operating temperature of the system. Because
Step 7: TTHERM for Temperature Channels
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exceeding any TTHERM limit runs all fans at 100%, it has very negative acoustic effects. Ultimately, this limit should be set up as a fail-safe, and one should ensure that it is not exceeded under normal system operating conditions. Note that TTHERM limits are non-maskable and affect the fan speed no matter how automatic fan control settings are configured. This allows some flexibility, because a TRANGE value can be selected based on its slope, while a hard limit (such as 70C), can be programmed as TMAX (the temperature at which the fan reaches full speed) by setting TTHERM to that limit (for example, 70C).
THERM Registers THERM Hysteresis
THERM hysteresis on a particular channel is configured via the hysteresis settings in the following section (0x6D and 0x6E). For example, setting hysteresis on the Remote 1 channel also sets the hysteresis on Remote 1 THERM.
Hysteresis Registers
Register 0x6D, Remote 1, Local Hysteresis Register Bits [7:4], Remote 1 Temperature Hysteresis (4C default) Bits [3:0], Local Temperature Hysteresis (4C default) Register 0x6E, Remote 2, PECI Temperature Hysteresis Register Bits [7:4], Remote 2 Temperature Hysteresis (4C default) Bits [3:0], PECI Temperature Hysteresis (4C default)
Register 0x6A, Remote 1 THERM Temperature Limit = 0x64 (100C default) Register 0x6B, Local THERM Temperature Limit = 0x64 (100C default) Register 0x6C, Remote 2 THERM Temperature Limit = 0x64 (100C default) Register 0x3D, PECI TCONTROL Limit = 0x00 (0C default)
Because each hysteresis setting is four bits, hysteresis values are programmable from 1C to 15C. It is not recommended that hysteresis values ever be programmed to 0C, because this disables hysteresis. In effect, this causes the fans to cycle (during a THERM event) between normal speed and 100% speed, or, while operating close to TMIN, between normal speed and off, creating unsettling acoustic noise.
TRANGE 100% PWM DUTYCYCLE 0% TMIN TTHERM
THERMAL CALIBRATION
100%
PWM MIN
PWM CONFIG PWM GENERATOR RAMP CONTROL (ACOUSTIC ENHANCEMENT) PWM1
TMIN REMOTE 2 = CPU TEMP
TRANGE
0% PWM MIN
TACHOMETER 1 MEASUREMENT PWM CONFIG PWM GENERATOR
TACH1 CPU FAN SINK RAMP CONTROL (ACOUSTIC ENHANCEMENT)
THERMAL CALIBRATION
100%
MUX
0% PWM MIN
PWM2
TMIN LOCAL = VRM TEMP
TRANGE
TACHOMETER 2 MEASUREMENT PWM CONFIG PWM GENERATOR
TACH2
THERMAL CALIBRATION
100%
RAMP CONTROL (ACOUSTIC ENHANCEMENT)
FRONT CHASSIS PWM3
TMIN REMOTE 1 = AMBIENT TEMP
TRANGE
0%
TACHOMETER 3 AND 4 MEASUREMENT
TACH3
Figure 59. How TTHERM Relates to Automatic Fan Control
REAR CHASSIS
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THYST is the amount of extra cooling a fan provides after the temperature measured has dropped back below TMIN before the fan turns off. The premise for temperature hysteresis (THYST) is that, without it, the fan would merely chatter, or cycle on and off regularly, whenever the temperature is hovering at about the TMIN setting. The THYST value chosen determines the amount of time needed for the system to cool down or heat up as the fan is turning on and off. Values of hysteresis are programmable in the range of 1C to 15C. Larger values of THYST prevent the fans from chattering on and off. The THYST default value is set at 4C.
TRANGE 100% PWM DUTYCYCLE
Step 8: THYST for Temperature Channels
The THYST setting applies not only to the temperature hysteresis for fan on/off, but the same setting is used for the TTHERM hysteresis value, described in the Step 7: TTHERM for Temperature Channels section. Therefore, programming Register 0x6D and Register 0x6E sets the hysteresis for both fan on/off and the THERM function. In some applications, it is required that fans not turn off below TMIN, but remain running at PWMMIN. Bits [7:5] of Enhanced Acoustics Register 1 (0x62) allow the fans to be turned off or to be kept spinning below TMIN. If the fans are always on, the THYST value has no effect on the fan when the temperature drops below TMIN.
0% TMIN TTHERM
THERMAL CALIBRATION
100%
PWM MIN
PWM CONFIG PWM GENERATOR RAMP CONTROL (ACOUSTIC ENHANCEMENT) PWM1
TMIN REMOTE 2 = CPU TEMP
TRANGE
0% PWM MIN
TACHOMETER 1 MEASUREMENT PWM CONFIG PWM GENERATOR
TACH1 CPU FAN SINK RAMP CONTROL (ACOUSTIC ENHANCEMENT)
THERMAL CALIBRATION
100%
MUX
0% PWM MIN
PWM2
TMIN LOCAL = VRM TEMP
TRANGE
TACHOMETER 2 MEASUREMENT PWM CONFIG PWM GENERATOR
TACH2
THERMAL CALIBRATION
100%
RAMP CONTROL (ACOUSTIC ENHANCEMENT)
FRONT CHASSIS PWM3
TMIN REMOTE 1 = AMBIENT TEMP
TRANGE
0%
TACHOMETER 3 AND 4 MEASUREMENT
TACH3
REAR CHASSIS
Figure 60. The THYST Value Applies to Fan On/Off Hysteresis and THERM Hysteresis THERM Hysteresis
Any hysteresis programmed via Register 0x6D and Register 0x6E also applies hysteresis on the appropriate THERM channel.
Enhanced Acoustics Register 1 (Register 0x62)
Bit 7 (MIN3) = 0, PWM3 is off (0% PWM duty cycle) when temperature is below TMIN - THYST.
Bit 7 (MIN3) = 1, PWM3 runs at PWM3 minimum duty cycle below TMIN - THYST. Bit 6 (MIN2) = 0, PWM2 is off (0% PWM duty cycle) when the temperature is below TMIN - THYST. Bit 6 (MIN2) = 1, PWM2 runs at PWM2 minimum duty cycle below TMIN - THYST.
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Bit 5 (MIN1) = 0, PWM1 is off (0% PWM duty cycle) when the temperature is below TMIN - THYST. Bit 5 (MIN1) = 1, PWM1 runs at PWM1 minimum duty cycle below TMIN - THYST.
Configuration Register 6 (Register 0x10)
Bit 0 (SLOW) = 1, slows the ramp rate for PWM changes associated with the Remote 1 temperature channel by 4. Bit 1 (SLOW) = 1, slows the ramp rate for PWM changes associated with the local temperature channel by 4. Bit 2 (SLOW) = 1, slows the ramp rate for PWM changes associated with the Remote 2 temperature channel by 4. Bit 7 (ExtraSlow) = 1, slows the ramp rate for all fans by a factor of 39.2%. The following sections list the ramp-up times when the SLOW bit is set for each temperature monitoring channel.
Enhanced Acoustics Register 1 (Register 0x62)
110 = 1.6 sec 111 = 0.8 sec When Bit 7 of Configuration Register 6 (0x10) = 1, the preceding ramp rates change to 000 = 52.2 sec 001 = 26.1 sec 010 = 17.4 sec 011 = 10.4 sec 100 = 6.5 sec 101 = 4.4 sec 110 = 2.2 sec 111 = 1.1 sec Setting the appropriate SLOW Bit 2, Bit 1, or Bit 0 of Configuration Register 6 (0x10) slows the ramp rate further by a factor of 4.
Programming the GPIOs
Bits [2:0] ACOU, selects the ramp rate for PWM outputs associated with the Remote Temperature 1 input. 000 = 37.5 sec 001 = 18.8 sec 010 = 12.5 sec 011 = 7.5 sec 100 = 4.7 sec 101 = 3.1 sec 110 = 1.6 sec 111 = 0.8 sec
Enhanced Acoustics Register 2 (Register 0x63)
The ADT7490 has two dedicated GPIOs (Pin 5 and Pin 6).The direction (input or output) and polarity (active high or active low) of the GPIOs is set in the GPIO Configuration Register (0x80). Bit 2 and Bit 3 of Register 0x80 also reflect the state of the GPIO pins when configured as inputs and assert the GPIO pins when configured as outputs.
XNOR Tree Test Mode
Bits [2:0] ACOU3, selects the ramp rate for PWM outputs associated with the local temperature channel. 000 = 37.5 sec 001 = 18.8 sec 010 = 12.5 sec 011 = 7.5 sec 100 = 4.7 sec 101 = 3.1 sec 110 = 1.6 sec 111 = 0.8 sec [6:4] ACOU2, selects the ramp rate for PWM outputs associated with the Remote Temperature 2 input. 000 = 37.5 sec 001 = 18.8 sec 010 = 12.5 sec 011 = 7.5 sec 100 = 4.7 sec 101 = 3.1 sec
The ADT7490 includes an XNOR tree test mode. This mode is useful for in-circuit test equipment at board-level testing. By applying stimulus to the pins included in the XNOR tree, it is possible to detect opens, or shorts, on the system board. The XNOR tree test is invoked by setting Bit 0 (XEN) of the XNOR Tree Test Enable register (Register 0x6F). Figure 61 shows the signals that are exercised in the XNOR tree test mode.
PWM2 PWM3
TACH1
TACH2
TACH3
TACH4
PWM1/XTO
Figure 61. XNOR Tree Test
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Register Tables
Table 20. ADT7490 Registers
Addr
0x10
R/W
R/W
Desc
Config. Reg. 6 Config. Reg. 7 Extended Revision PECI1 PECI2 PECI3 IMON Meas. VTT Meas. Extended Resolution 3 +2.5VIN Meas. VCCP Meas. VCC Meas. +5VIN Meas. +12VIN Meas. Remote 1 Temp. Local Temp. Remote 2 Temp. TACH1 Low Byte TACH1 High Byte TACH2 Low Byte TACH2 High Byte TACH3 Low Byte TACH3 High Byte TACH4 Low Byte TACH4 High Byte PWM1 Current Duty Cycle PWM2 Current Duty Cycle PWM3 Current Duty Cycle PECI0
Bit 7
Extra Slow RES RES 7 7 7 9 9 IMON
Bit 6
VCCP Low RES RES 6 6 6 8 8 IMON
Bit 5
Res
Bit 4
Res
Bit 3
Res
Bit 2
SLOW Remote 2 Vx1 RES 2 2 2 4 4 RES
Bit 1
SLOW Local FSPD RES 1 1 1 3 3 RES
Bit 0
SLOW Remote 1 THERM Hys - 0 0 0 2 2 RES
Default
0x00
Lockable
Yes
0x11 0x12 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F
R/W R R R R R R R
RES RES 5 5 5 7 7 VTT
TODIS RES 4 4 4 6 6 VTT
FSPDIS RES 3 3 3 5 5 RES
0x00 - 0x80 0x80 0x80 0x00 0x00 0x00
Yes - - - - - - -
0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30
R R R R R R R R R R R R R R R R R/W
9 9 9 9 9 9 9 9 7 15 7 15 7 15 7 15 7
8 8 8 8 8 8 8 8 6 14 6 14 6 14 6 14 6
7 7 7 7 7 7 7 7 5 13 5 13 5 13 5 13 5
6 6 6 6 6 6 6 6 4 12 4 12 4 12 4 12 4
5 5 5 5 5 5 5 5 3 11 3 11 3 11 3 11 3
4 4 4 4 4 4 4 4 2 10 2 10 2 10 2 10 2
3 3 3 3 3 3 3 3 1 9 1 9 1 9 1 9 1
2 2 2 2 2 2 2 2 0 8 0 8 0 8 0 8 0
0x00 0x00 0x00 0x00 0x00 0x80 0x80 0x80 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xFF
- - - - - - - - - - - - - - - - -
0x31
R/W
7
6
5
4
3
2
1
0
0xFF
-
0x32
R/W
7
6
5
4
3
2
1
0
0xFF
-
0x33
R
7
6
5
4
3
2
1
0
0x80
-
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Table 20. ADT7490 Registers
Addr
0x34 0x35 0x36
R/W
R/W R/W R/W
Desc
PECI Low Limit PECI High Limit PECI Config. Register 1 Max PWM1 Duty Cycle Max PWM2 Duty Cycle Max PWM3 Duty Cycle PECI TMIN PECI TRANGE/ Enhanced Acoustics PECI TCONTROL Limit Company ID No. Version Config. Register 1 Interrupt Status 1 Interrupt Status 2 Interrupt Status 3
Bit 7
7 7 RES
Bit 6
6 6 RES
Bit 5
5 5 RES
Bit 4
4 4 RE- PLACE 4
Bit 3
3 3 DOM0
Bit 2
2 2 AVG2
Bit 1
1 1 AVG1
Bit 0
0 0 AVG0
Default
0x81 0x00 0x00
Lockable
- - Yes
0x38
R/W
7
6
5
3
2
1
0
0xFF
Yes
0x39
R/W
7
6
5
4
3
2
1
0
0xFF
Yes
0x3A
R/W
7
6
5
4
3
2
1
0
0xFF
Yes
0x3B 0x3C
R/W R/W
7 RANGE
6 RANGE
5 RANGE
4 RANGE
3 ENP
2 ACOU
1 ACOU
0 ACOU
0xE0 0xC0
Yes Yes
0x3D
R/W
7
6
5
4
3
2
1
0
0x00
Yes
0x3E 0x3F 0x40
R R R/W
7 VER3 RES
6 VER2 RES
5 VER1 THERM in Manual LT FAN4/ THERM RES
4 VER0 PECI Monitor R1T FAN3 RES
3 4-Wire Fan Boost +5VIN FAN2 OVT (THERM Temp Limit) 3 3 3 3 3 3 3 3 3 3 3
2 PECI RDY
1 REV1 LOCK
0 REV0 STRT
0x41 0x06X 0x04
- - Yes
0x41 0x42 0x43
R R R
OOL D2 FAULT OOL
R2T D1 FAULT RES
VCC FAN1 COMM
VCCP OOL DATA
+2.5VIN/ THERM +12VIN PECI0
0x00 0x00 0x00
- - -
0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
+2.5VIN Low Limit +2.5VIN High Limit VCCP Low Limit VCCP High Limit VCC Low Limit VCC High Limit +5VIN Low Limit +5VIN High Limit +12VIN Low Limit +12VIN High Limit Remote 1 Temp Low Limit
7 7 7 7 7 7 7 7 7 7 7
6 6 6 6 6 6 6 6 6 6 6
5 5 5 5 5 5 5 5 5 5 5
4 4 4 4 4 4 4 4 4 4 4
2 2 2 2 2 2 2 2 2 2 2
1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0
0x00 0xFF 0x00 0xFF 0x00 0xFF 0x00 0xFF 0x00 0xFF 0x81
- - - - - - - - - - -
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Table 20. ADT7490 Registers
Addr
0x4F
R/W
R/W
Desc
Remote 1 Temp High Limit Local Temp Low Limit Local Temp High Limit Remote 2 Temp Low Limit Remote 2 Temp High Limit TACH1 Min Low Byte TACH1 Min High Byte TACH2 Min Low Byte TACH2 Min High Byte TACH3 Min Low Byte TACH3 Min High Byte TACH4 Min Low Byte TACH4 Min High Byte PWM1 Config. Register PWM2 Config. Register PWM3 Config. Register Remote 1 TRANGE/ PWM1 Frequency Local TRANGE/P WM2 Frequency Remote 2 TRANGE/P WM3 Frequency Enhanced Acoustics Reg. 1 Enhanced Acoustics Reg. 2
Bit 7
7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
0
Default
0x7F
Lockable
-
0x50
R/W
7
6
5
4
3
2
1
0
0x81
-
0x51
R/W
7
6
5
4
3
2
1
0
0x7F
-
0x52
R/W
7
6
5
4
3
2
1
0
0x81
-
0x53
R/W
7
6
5
4
3
2
1
0
0x7F
-
0x54
R/W
7
6
5
4
3
2
1
0
0xFF
-
0x55
R/W
15
14
13
12
11
10
9
8
0xFF
-
0x56
R/W
7
6
5
4
3
2
1
0
0xFF
-
0x57
R/W
15
14
13
12
11
10
9
8
0xFF
-
0x58
R/W
7
6
5
4
3
2
1
0
0xFF
-
0x59
R/W
15
14
13
12
11
10
9
8
0xFF
-
0x5A
R/W
7
6
5
4
3
2
1
0
0xFF
-
0x5B
R/W
15
14
13
12
11
10
9
8
0xFF
-
0x5C
R/W
BHVR
BHVR
BHVR
INV
ALT
SPIN
SPIN
SPIN
0x62
Yes
0x5D
R/W
BHVR
BHVR
BHVR
INV
ALT
SPIN
SPIN
SPIN
0x62
Yes
0x5E
R/W
BHVR
BHVR
BHVR
INV
ALT
SPIN
SPIN
SPIN
0x62
Yes
0x5F
R/W
RANGE
RANGE
RANGE
RANGE
HF/LF
FREQ
FREQ
FREQ
0xC4
Yes
0x60
R/W
RANGE
RANGE
RANGE
RANGE
HF/LF
FREQ
FREQ
FREQ
0xC4
Yes
0x61
R/W
RANGE
RANGE
RANGE
RANGE
HF/LF
FREQ
FREQ
FREQ
0xC4
Yes
0x62
R/W
MIN3
MIN2
MIN1
SYNC
EN1
ACOU
ACOU
ACOU
0x00
Yes
0x63
R/W
EN2
ACOU2
ACOU2
ACOU2
EN3
ACOU3
ACOU3
ACOU3
0x00
Yes
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ADT7490
Table 20. ADT7490 Registers
Addr
0x64
R/W
R/W
Desc
PWM1 Min Duty Cycle PWM2 Min Duty Cycle PWM3 Min Duty Cycle Remote 1 Temp. TMIN Local Temp. TMIN Remote 2 Temp. TMIN Remote 1 THERM Temp. Limit Local THERM Temp. Limit Remote 2 THERM Temp. Limit Remote 1 and Local Temp./ TMIN Hysteresis Remote 2 and PECI Temp./ TMIN Hysteresis XNOR Tree Test Enable Remote 1 Temp Offset Local Temp. Offset Remote 2 Temp. Offset Config. Reg. 2 Interrupt Mask Reg. 1 Interrupt Mask Reg. 2 Extended Resolution 1 Extended Resolution 2 Config. Reg. 3
Bit 7
7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
0
Default
0x80
Lockable
Yes
0x65
R/W
7
6
5
4
3
2
1
0
0x80
Yes
0x66
R/W
7
6
5
4
3
2
1
0
0x80
Yes
0x67
R/W
7
6
5
4
3
2
1
0
0x5A
Yes
0x68
R/W
7
6
5
4
3
2
1
0
0x5A
Yes
0x69
R/W
7
6
5
4
3
2
1
0
0x5A
Yes
0x6A
R/W
7
6
5
4
3
2
1
0
0x64
Yes
0x6B
R/W
7
6
5
4
3
2
1
0
0x64
Yes
0x6C
R/W
7
6
5
4
3
2
1
0
0x64
Yes
0x6D
R/W
HYSR1
HYSR1
HYSR1
HYSR1
HYSL
HYSL
HYSL
HYSL
0x44
Yes
0x6E
R/W
HYSR2
HYSR2
HYSR2
HYSR2
HYSP
HYSP
HYSP
HYSP
0x44
Yes
0x6F
R/W
RES
RES
RES
RES
RES
RES
RES
XEN
0x00
Yes
0x70
R/W
7
6
5
4
3
2
1
0
0x00
Yes
0x71
R/W
7
6
5
4
3
2
1
0
0x00
Yes
0x72
R/W
7
6
5
4
3
2
1
0
0x00
Yes
0x73 0x74
R/W R/W
Shutdo wn OOL
CONV R2T
ATTN LT
AVG R1T
Fan3 Detect +5VIN
Fan2 Detect VCC
Fan1 Detect VCCP
Fan PresDT +2.5VIN/ THERM +12VIN/ VC +2.5VIN
0x00 0x00
Yes -
0x75
R/W
D2 FAULT +5VIN
D1 FAULT +5VIN
FAN4/ THERM VCC
FAN3
FAN2
FAN1
OOL
0x00
-
0x76
R
VCC
VCCP
VCCP
+2.5VIN
0x00
-
0x77
R
TDM2
TDM2
LTMP
LTMP
TDM1
TDM1
+12VIN
+12VIN
0x00
-
0x78
R/W
DC4
DC3
DC2
DC1
FAST
BOOST
THERM/ +2.5VIN
ALERT Enable
0x00
Yes
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ADT7490
Table 20. ADT7490 Registers
Addr
0x79
R/W
R
Desc
THERM Timer Status THERM Timer Limit TACH Pulses per Revolution Config. Register 5
Bit 7
TMR
Bit 6
TMR
Bit 5
TMR
Bit 4
TMR
Bit 3
TMR
Bit 2
TMR
Bit 1
TMR
Bit 0
ASRT/ TMR0 LIMT
Default
0x00
Lockable
-
0x7A
R/W
LIMT
LIMT
LIMT
LIMT
LIMT
LIMT
LIMT
0x00
-
0x7B
R/W
FAN4
FAN4
FAN3
FAN3
FAN2
FAN2
FAN1
FAN1
0x55
-
0x7C
R/W
R2 THERM Output Only BpAtt +12VIN
Local THERM Output Only BpAtt +5VIN
R1 THERM Output Only BpAtt VCCP
PECI R1 THERM Output Only BpAtt +2.5VIN
RES
RES
Temp Offset
TWOS COMPL
0x01
Yes
0x7D
R/W
Config. Register 4 Test 1 Test 2 GPIO Config. Register Interrupt Status 4 Interrupt Mask 3 Interrupt Mask 4 VTT Low Limit IMON Low Limit VTT High Limit IMON High Limit PECI Config. 2 TEST 3 PECI Operating Point Remote 1 Operating Point Local Temp. Operating Point Remote 2 Operating Point Dynamic TMIN Control Reg. 1 Dynamic TMIN Control Reg. 2 Dynamic TMIN Control Reg. 3
Max/Full on THERM
THERM Disable
Pin 14 Func
Pin 14 Func
0x00
Yes
0x7E 0x7F 0x80
R R R/W
Do not write to this register Do not write to this register GPIO1 DIR VTT OOL VTT 7 7 7 7 #CPU GPIO2 DIR IMON RES IMON 6 6 6 6 #CPU GPIO1 POL PECI3 RES PECI3 5 5 5 5 DOM1 GPIO2 POL PECI2 RES PECI2 4 4 4 4 DOM2 GPIO1 GPIO2 RES RES
0x00 0x00 0x00
Yes Yes -
0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A
R R/W R/W R/W R/W R/W R/W R/W R R/W
PECI1 OVT PECI1 3 3 3 3 DOM3
RES COMM RES 2 2 2 2 RES
RES DATA RES 1 1 1 1 RES
RES PECI0 RES 0 0 0 0 RES
0x00 0x00 0x00 0x00 0x00 0xFF 0xFF 0x00 0x00
- - - Yes Yes Yes Yes Yes Yes Yes
Do not write to this register 7 6 5 4 3 2 1 0
0xFB
0x8B
R/W
7
6
5
4
3
2
1
0
0x64
Yes
0x8C
R/W
7
6
5
4
3
2
1
0
0x64
Yes
0x8D
R/W
7
6
5
4
3
2
1
0
0x64
Yes
0x8E
R/W
R2T
LT
R1T
PHTR2
PHTL
PHTR1
VCCPLO
CYR2
0x00
Yes
0x8F
R/W
CYR2
CYR2
CYL
CYL
CYL
CYR1
CYR1
CYR1
0x00
Yes
0x90
R/W
PECI
PHTP
CYP
CYP
CYP
RES
RES
RES
0x00
Yes
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ADT7490
Table 20. ADT7490 Registers
Addr
0x94
R/W
R/W
Desc
PECI0 Temp. Offset PECI1 Temp. Offset PECI2 Temp. Offset PECI3 Temp. Offset
Bit 7
7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
0
Default
0x00
Lockable
Yes
0x95
R/W
7
6
5
4
3
2
1
0
0x00
Yes
0x96
R/W
7
6
5
4
3
2
1
0
0x00
Yes
0x97
R/W
7
6
5
4
3
2
1
0
0x00
Yes
-
0x41
-
-
0x74
OOL
R2T
LT
R1T
+5VIN
VCC
VCCP
+2.5VIN/ THERM
Table 21. Register 0x10 -- Configuration Register 6 (Power-On Default = 0x00)
Bit No. [0] [1] [2] [3] [4] [5] [6] Mnemonic SLOW Remote 1 SLOW Local SLOW Remote 2 Res Res Res VCCP Low R/W (Note 1) R/W R/W R/W N/A N/A N/A R/W Description When this bit is set, fan smoothing times are multiplied x4 for Remote 1 temperature channel (as defined in Register 0x62). When this bit is set, fan smoothing times are multiplied x4 for local temperature channel (as defined in Register 0x63). When this bit is set, fan smoothing times are multiplied x4 for Remote 2 temperature channel (as defined in Register 0x63). Reserved. Reserved. Reserved. VCCP Low = 1. When the power is supplied from 3.3 V STANDBY and the core voltage (VCCP) drops below its VCCP low limit value (Register 0x46), the following occurs: Status Bit 1 in Status Register 1 is set. SMBALERT is generated, if enabled. PROCHOT monitoring is disabled. Everything is re-enabled once VCCP increases above the VCCP low limit. When VCCP increases above the low limit: PROCHOT monitoring is enabled. Fans return to their programmed state after a spin-up cycle. When this bit is set, all fan smoothing times are increased by a further 39.2%
[7]
ExtraSlow
R/W
1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any subsequent attempts to write to this register fail.
Table 22. Register 0x11 -- Configuration Register 7 (Power-On Default = 0x00)
Bit No. [0] [1] [2] Mnemonic THERMHys FSPD Vx1 R/W (Note 1) R/W R/W R/W Description THERM hysteresis is enabled by default. Setting this bit to 1 disables THERM hysteresis. When set to 1, this bit runs all fans at maximum speed as programmed in the maximum PWM duty cycle registers (0x38 to 0x3A). Power-on default = 0. This bit is not locked at any time. BIOS should set this bit to 1 when the ADT7490 is configured to measure current from an Analog Devices ADOPT VRM controller and to measure the CPU core voltage. This bit allows monitoring software to display CPU watts usage. (Lockable.) Logic 1 disables fan spin-up for two TACH pulses. Instead, the PWM outputs go high for the entire fan spin-up timeout selected. When this bit is set to 1, the SMBus timeout feature is disabled. In this state, if at any point during an SMBus transaction involving the ADT7490 activity ceases for more than 35 ms, the ADT7490 assumes the bus is locked and releases the bus. This allows the ADT7490 to be used with SMBus controllers that cannot handle SMBus timeouts. (Lockable.) Reserved. Do not write to these bits.
[3] [4]
FSPDIS TODIS
R/W R/W
[7:5]
RES
N/A
1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any subsequent attempts to write to this register fail.
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ADT7490
Table 23. PECI Reading Registers (Power-On Default = 0x80)
Register Address 0x33 0x1A 0x1B 0x1C R/W Read-only Read-only Read-only Read-only Description PECI0: This register reads the eight bits representative of PECI Client Address 0x30. PECI1: This register reads the eight bits representative of PECI Client Address 0x31. PECI2: This register reads the eight bits representative of PECI Client Address 0x32. PECI3: This register reads the eight bits representative of PECI Client Address 0x33.
Table 24. IMON/VTT Reading Registers (Power-On Default = 0x00)
Register Address 0x1D 0x1E R/W Read-only Read-only Description Reflects the voltage measurement at the IMON input on Pin 19 (8 MSBs of reading). Input range of 0 V to 2.25 V. Reflects the voltage measurement at the VTT input on Pin 8 (8 MSBs of reading). Input range of 0 V to 2.25 V.
Table 25. Register 0x1F -- Extended Resolution 3 (Power-On Default = 0x00)
Bit No. [3:0] [5:4] [7:6] R/W Read-only Read-only Read-only Reserved. Hold the two LSBs of the 10-bit VTT measurement. Hold the two LSBs of the 10-bit IMON measurement. Description
Table 26. Voltage Reading Registers (Power-On Default = 0x00) (Note 1)
Register Address 0x20 0x21 0x22 0x23 0x24 R/W Read-only Read-only Read-only Read-only Read-only Description Reflects the voltage measurement at the 2.5 VIN input on Pin 22 (8 MSBs of reading). Reflects the voltage measurement (Note 2) at the VCCP input on Pin 23 (8 MSBs of reading). Reflects the voltage measurement (Note 3) at the VCC input on Pin 4 (8 MSBs of reading). Reflects the voltage measurement at the 5 VIN input on Pin 20 (8 MSBs of reading). Reflects the voltage measurement at the 12 VIN input on Pin 21 (8 MSBs of reading).
1. If the extended resolution bits of these readings are also being read, the extended resolution registers (Register 0x76, Register 0x77) must be read first. Once the extended resolution registers have been read, the associated MSB reading registers are frozen until read. Both the extended resolution registers and the MSB registers are frozen. 2. If VCCP Low (Bit 6 of 0x10) is set, VCCP can control the sleep state of the ADT7490. 3. VCC (Pin 4) is the supply voltage for the ADT7490.
Table 27. Temperature Reading Registers (Power-On Default = 0x80) (Note 1 and 2)
Register Address 0x25 0x26 0x27 R/W Read-only Read-only Read-only Description Remote 1 temperature reading (Note 3 and 4) (8 MSBs of reading). Local temperature reading (8 MSBs of reading). Remote 2 temperature reading (Note 3 and 4) (8 MSBs of reading).
1. If the extended resolution bits of these readings are also being read, the extended resolution registers (Register 0x76, Register 0x77) must be read first. Once the extended resolution registers have been read, all associated MSB reading registers are frozen until read. Both the extended resolution registers and the MSB registers are frozen. 2. These temperature readings can be in twos complement or Offset 64 format; this interpretation is determined by Bit 0 of Configuration Register 5 (0x7C). 3. In twos complement mode, a temperature reading of -128C (0x80) indicates a diode fault (open or short) on that channel. 4. In Offset 64 mode, a temperature reading of -64C (0x00) indicates a diode fault (open or short) on that channel.
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ADT7490
Table 28. Fan Tachometer Reading Registers (Power-On Default = 0x00) (Note 1)
Register Address 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F R/W Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only TACH1 low byte. TACH1 high byte. TACH2 low byte. TACH2 high byte. TACH3 low byte. TACH3 high byte. TACH4 low byte. TACH4 high byte. Description
1. These registers count the number of 11.11 ms periods (based on an internal 90 kHz clock) that occur between a number of consecutive fan TACH pulses (default = 2). The number of TACH pulses used to count can be changed using the TACH Pulses per Revolution register (Register 0x7B). This allows the fan speed to be accurately measured. Because a valid fan tachometer reading requires that two bytes be read, the low byte must be read first. Both the low and high bytes are then frozen until read. At power-on, these registers contain 0x0000 until the first valid fan TACH measurement is read into these registers. This prevents false interrupts from occurring while the fans are spinning up. A count of 0xFFFF indicates that a fan is one of the following: stalled or blocked (object jamming the fan), failed (internal circuitry destroyed), or not populated. (The ADT7490 expects to see a fan connected to each TACH. If a fan is not connected to that TACH, its TACH minimum high and low bytes should be set to 0xFFFF.) An alternate function, for example, is TACH4 reconfigured as the THERM pin.
Table 29. Current PWM Duty Cycle Registers (Power-On Default = 0xFF) (Note 1)
Register Address 0x30 0x31 0x32 R/W R/W R/W R/W Description PWM1 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF). PWM2 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF). PWM3 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF).
1. These registers reflect the PWM duty cycle driving each fan at any given time. When in automatic fan speed control mode, the ADT7490 reports the PWM duty cycles back through these registers. The PWM duty cycle values vary according to temperature in automatic fan speed control mode. During fan startup, these registers report back 0x00. In manual mode, the PWM duty cycle outputs can be set to any duty cycle value by writing to these registers.
Table 30. Register 0x33 -- PECI0 Reading Register (Power-On Default = 0x80)
Register Address 0x33 R/W Read-only Description PECI0: This register reads the eight bits representative of PECI Client Address 0x30.
Table 31. PECI Limit Registers
Register Address 0x34 0x35 R/W R/W R/W PECI low limit. PECI high limit. Description Power-On Default 0x81 0x00
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ADT7490
Table 32. Register 0x36 -- PECI Configuration Register 1 (Power-On Default = 0x00)
Bit No. [2:0] Mnemonic AVG[2:0] R/W (Note 1) R/W Description PECI Smoothing Interval. These bits set the duration over which smoothing is carried out on the PECI data read. Note that the PECI smoothing interval is equal to the PECI register update interval. The smoothing interval is calculated using the following formula: Smooth Interval = #reads x (tBIT x 67 x #CPU + tIDLE) where: #reads is the number of readings defined below. tBIT is the negotiated bit rate. 67 is the number of bits in each PECI reading. #CPU is the number of CPUs providing PECI data (1 to 4). tIDLE = 14 ms, the delay between consecutive reads. Bit Code 000 001 010 011 100 101 110 111 [3] DOM0 R/W Number of PECI Readings 16 2048 4096 8192 16384 32768 65536 Reserved
CPU Domain Count information. Set to 0 indicates that CPU 1 associated with the PECI0 reading has a single domain (default). Set to 1 indicates that the system CPU 1 contains two domains. If this bit is set to 0, it indicates that the ADT7490 is operating in standard mode. If this bit is set to 1, the Remote 1 Temperature register (Register 0x25) is overwritten by PECI0 information (Register 0x33) and vice versa. Note that in this mode, all associated user programmable limit and fan control registers are also swapped and should be programmed in the appropriate PECI or absolute temperature format. Reserved.
[4]
REPLACE
R/W
[7:5]
RES
R
1. These registers become read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any subsequent attempts to write to these registers fail.
Table 33. Maximum PWM Duty Cycle (Power-On Default = 0xFF) (Note 1)
Register Address 0x38 0x39 0x3A R/W (Note 2) R/W R/W R/W Description Maximum duty cycle for PWM1 output, default = 100% (0xFF). Maximum duty cycle for PWM2 output, default = 100% (0xFF). Maximum duty cycle for PWM3 output, default = 100% (0xFF).
1. These registers set the maximum PWM duty cycle of the PWM output. 2. These registers become read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any subsequent attempts to write to these registers fail.
Table 34. PECI TMIN Register (Power-On Default = 0xE0, Value = -32)
Register Address 0x3B R/W (Note 1) R/W Description PECI TMIN. When the PECI measurement exceeds PECI TMIN, the appropriate fans run at PWMMIN and increase according to the automatic fan speed control slope.
1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set. Any further attempts to write to this register have no effect.
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ADT7490
Table 35. Register 0x3C -- PECI TRANGE/Enhanced Acoustics Register (Power-On Default = 0xC0)
Bit No. [2:0] Mnemonic ACOU R/W (Note 1) R/W Description Assuming that PWMx is associated with the PECI channel, these bits define the maximum rate of change of the PWMx output for PECI temperature-related changes. Instead of the fan speed jumping instantaneously to its newly determined speed, it ramps gracefully at the rate determined by these bits. This feature ultimately enhances the acoustics of the fan. The smoothing times below are based on a refresh rate of the round robin cycle. The PECI data, for 0% to 100%, must be multiplied each time by: PECI Refresh Rate Round Robin Cycle where the PECI refresh rate is defined in Register 0x36 and the round robin cycle is typically 165 ms. When Bit 7 of Configuration Register 6 (0x10) is 0 Bit Code 000 = 1 001 = 2 010 = 3 011 = 4 100 = 8 101 = 12 110 = 24 111 = 48 [2:0] ACOU R/W Bit Code 000 = 1 001 = 2 010 = 3 011 = 4 100 = 8 101 = 12 110 = 24 111 = 48 [3] [7:4] ENP RANGE R/W R/W Time for 0% to 100% 37.5 sec 18.8 sec 12.5 sec 7.5 sec 4.7 sec 3.1 sec 1.6 sec 0.8 sec Time for 0% to 100% 52.2 sec 26.1 sec 17.4 sec 10.4 sec 6.5 sec 4.4 sec 2.2 sec 1.1 sec
When Bit 7 of Configuration Register 6 (0x10) is 1
When this bit is set to 1, smoothing is enabled on the PECI channel allowing enhanced acoustics on the associated PWM output. These bits determine the PWM duty cycle vs. the temperature range for automatic fan control. Bit Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Temperature 2C 2.5C 3.33C 4C 5C 6.67C 8C 10C 13.33C 16C 20C 26.67C 32C (default) 40C 53.33C 80C
1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any subsequent attempts to write to this register fail.
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ADT7490
Table 36. TCONTROL Limit Register (Power-On Default = 0x00) (Note 1)
Register Address 0x3D R/W (Note 2) R/W PECI TCONTROL limit. Description
1. If any PECI reading exceeds the TCONTROL limit, all PWM outputs drive their fans at 100% duty cycle. This is a fail-safe mechanism incorporated to cool the system in the event of a critical overtemperature. It also ensures some level of cooling in the event that software or hardware locks up. If set to 0x80, this feature is disabled. The PWM output remains at 100% until the temperature drops below TCONTROL limit - hysteresis. 2. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any further attempts to write to this register have no effect.
Table 37. Register 0x3F -- Version Register
Bit No. [1:0] Mnemonic REV[1:0] R/W Read-only Description These two bits indicate the ADT7490 silicon revision number. 0x00 indicates Revision 0, 0x01 indicates Revision 1, and so on. 0x11 indicates that further revision information can be found in the "Extended Revision" register (0x12). The revision number is then found by adding 0x11 to the contents of the extended revision register. This bit is set to 1 indicating that the ADT7490 supports the PECI interface. This bit is set to 1 indicating that the ADT7490 may be configured to drive 4-wire fans using high frequency PWM. These bits indicate the version number of the device. This is set to 6, indicating that the ADT7490 is part of the Heceta 6 ASIC family.
[2] [3] [7:4]
PECI 4-Wire VER[3:0]
Read-only Read-only Read-only
Table 38. Register 0x40 -- Configuration Register 1 (Power-On Default = 0x04)
Bit No. [0] Mnemonic STRT (Notes 2, 3) R/W (Note 1) R/W Description Logic 1 enables monitoring and PWM control outputs based on the limit settings programmed. Logic 0 disables monitoring and PWM control is based on the default powerup limit settings. Note that the limit values programmed are preserved even if a Logic 0 is written to this bit and the default settings are enabled. This bit does not become locked once Bit 1 (LOCK bit) is set. Logic 1 locks all limit values to their current settings. Once this bit is set, all lockable registers become read-only and cannot be modified until the ADT7490 is powered down and powered up again. This prevents rogue programs such as viruses from modifying critical system limit settings. (Lockable.) This bit is set to 1 by the ADT7490 to indicate that the device is fully powered up and ready to begin system monitoring. When this bit is set to Logic 1, all PWM outputs go to 100% regardless of other fan speed configurations and automatic fan speed control settings. When this bit is set to 0, the fan speed control returns to the fan speed setting calculated by the preprogrammed fan speed control settings. This bit remains writable after the LOCK bit is set. Set this bit to Logic 1 to enable CPU thermal monitoring via PECI interface. This bit becomes read-only when the LOCK bit is set. When this bit is set to Logic 1, THERM is enabled so that the fans go to 100% duty cycle on a THERM or TCONTROL assertion overriding any other fan setting, even when the PWMs are configured for manual mode, or disabled. This bit becomes read-only when the LOCK bit is set. Reserved.
[1]
LOCK
Write once
[2] [3]
RDY Fan Boost
Read-only R/W
[4] [5]
PECI Monitor THERM in Manual RES
R/W R/W
[7:6]
Read-only
1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any subsequent attempts to write to this register fail. 2. Bit 0 (STRT) of Configuration Register 1 (0x40) remains writable after the LOCK bit is set. 3. When monitoring (STRT) is disabled, PWM outputs always go to 100% for thermal protection.
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ADT7490
Table 39. Register 0x41 -- Interrupt Status Register 1 (Power-On Default = 0x00)
Bit No. [0] Mnemonic +2.5 VIN/ THERM VCCP VCC +5 VIN R1T LT R2T OOL R/W Read-only Description +2.5 VIN = 1 indicates that the 2.5 VIN high or low limit has been exceeded. This bit is cleared on a read of the status register only if the error condition has subsided. If Pin 22 is configured as THERM, this bit is asserted when the timer limit has been exceeded. VCCP = 1 indicates that the VCCP high or low limit has been exceeded. This bit is cleared on a read of the status register only if the error condition has subsided. VCC = 1 indicates that the VCC high or low limit has been exceeded. This bit is cleared on a read of the status register only if the error condition has subsided. +5 VIN = 1 indicates that the 5 VIN high or low limit has been exceeded. This bit is cleared on a read of the status register only if the error condition has subsided. R1T = 1 indicates that the Remote 1 low or high temperature has been exceeded. This bit is cleared on a read of the status register only if the error condition has subsided. LT = 1 indicates that the local low or high temperature has been exceeded. This bit is cleared on a read of the status register only if the error condition has subsided. R2T = 1 indicates that the Remote 2 low or high temperature has been exceeded. This bit is cleared on a read of the status register only if the error condition has subsided. OOL = 1 indicates that an out-of-limit event has been latched in Interrupt Status Register 2 (0x42). This bit is a logical OR of all status bits in Interrupt Status Register 2. Software can test this bit in isolation to determine whether any of the voltage, temperature, or fan speed readings represented by Interrupt Status Register 2 are out-of-limit, which eliminates the need to read Interrupt Status Register 2 during every interrupt or polling cycle.
[1] [2] [3] [4] [5] [6] [7]
Read-only Read-only Read-only Read-only Read-only Read-only Read-only
Table 40. Register 0x42 -- Interrupt Status Register 2 (Power-On Default = 0x00)
Bit No. [0] [1] Mnemonic +12 VIN OOL R/W Read-only Read-only Description +12 VIN = 1 indicates that the 12 VIN high or low limit has been exceeded. This bit is cleared on a read of the status register only if the error condition has subsided. OOL = 1 indicates that an out-of-limit event has been latched in Interrupt Status Register 3 (0x43). This bit is a logical OR of all status bits in Interrupt Status Register 3. Software can test this bit in isolation to determine whether any of the voltage, temperature, or fan speed readings represented by Interrupt Status Register 3 are out-of-limit, which eliminates the need to read Interrupt Status Register 3 during every interrupt or polling cycle. FAN1 = 1 indicates that Fan 1 has dropped below minimum speed or has stalled. This bit is not set when the PWM1 output is off. FAN2 = 1 indicates that Fan 2 has dropped below minimum speed or has stalled. This bit is not set when the PWM2 output is off. FAN3 = 1 indicates that Fan 3 has dropped below minimum speed or has stalled. This bit is not set when the PWM3 output is off. When Pin 14 is programmed as a TACH4 input, FAN4 = 1 indicates that Fan 4 has dropped below minimum speed or has stalled. This bit is not set when the PWM3 output is off. If Pin 14 is configured as the THERM timer input for THERM monitoring, this bit is set when the THERM assertion time exceeds the limit programmed in the THERM timer limit register (Register 0x7A). D1 FAULT = 1 indicates either an open or short circuit on the Thermal Diode 1 inputs. D2 FAULT = 1 indicates either an open or short circuit on the Thermal Diode 2 inputs.
[2] [3] [4] [5]
FAN1 FAN2 FAN3 FAN4/ THERM
Read-only Read-only Read-only Read-only
[6] [7]
D1 FAULT D2 FAULT
Read-only Read-only
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Table 41. Register 0x43 -- Interrupt Status Register 3 (Power-On Default = 0x00)
Bit No. [0] Mnemonic PECI0 R/W Read-only Description A Logic 1 indicates that the PECI high or low limit has been exceeded by the PECI value from PECI Client Address 0x30. This bit is cleared on a read of the status register only if the error condition has subsided. A Logic 1 indicates that valid PECI data cannot be obtained for the processor and a specified error code has been recorded. A Logic 1 indicates that there is a communications error (for example, invalid FCS) on the PECI interface. OVT = 1 indicates that one of the THERM overtemperature limits has been exceeded. This bit is cleared on a read of the status register when the temperature drops below THERM - THYST. Reserved. OOL = 1 indicates that an out-of-limit event has been latched in Interrupt Status Register 4 (0x81). This bit is a logical OR of all status bits in Interrupt Status Register 4. Software can test this bit in isolation to determine whether any of the voltage, temperature, or fan speed readings represented by Interrupt Status Register 4 are out-of-limit, which eliminates the need to read Interrupt Status Register 4 during every interrupt or polling cycle.
[1] [2] [3]
DATA COMM OVT (THERM Temp Limit) RES OOL
Read-only Read-only Read-only
[6:4] [7]
Read-only Read-only
Table 42. Voltage Limit Registers (Note 1)
Register Address 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description (Note 2) +2.5 VIN low limit. +2.5 VIN high limit. VCCP low limit. VCCP high limit. VCC low limit. VCC high limit. +5 VIN low limit. +5 VIN high limit. +12 VIN low limit. +12 VIN high limit. Power-On Default 0x00 0xFF 0x00 0xFF 0x00 0xFF 0x00 0xFF 0x00 0xFF
1. Setting the Configuration Register 1 (0x40) LOCK bit has no effect on these registers. 2. High limits: An interrupt is generated when a value exceeds its high limit (> comparison). Low limits: An interrupt is generated when a value is equal to or below its low limit ( comparison).
Table 43. Temperature Limit Registers (Note 1)
Register Address 0x4E 0x4F 0x50 0x51 0x52 0x53 R/W R/W R/W R/W R/W R/W R/W Description (Note 2) Remote 1 temperature low limit. Remote 1 temperature high limit. Local temperature low limit. Local temperature high limit. Remote 2 temperature low limit. Remote 2 temperature high limit. Power-On Default 0x81 0x7F 0x81 0x7F 0x81 0x7F
1. Exceeding any of these temperature limits by 1C causes the appropriate status bit to be set in the interrupt status register. Setting the Configuration Register 1 (0x40) LOCK bit has no effect on these registers. 2. High limits: An interrupt is generated when a value exceeds its high limit (> comparison). Low limits: An interrupt is generated when a value is equal to or below its low limit ( comparison).
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Table 44. Fan Tachometer Limit Registers (Note 1)
Register Address 0x34 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W PECI low limit. TACH1 minimum low byte. TACH1 minimum high byte/single-channel ADC channel select. TACH2 minimum low byte. TACH2 minimum high byte. TACH3 minimum low byte. TACH3 minimum high byte. TACH4 minimum low byte. TACH4 minimum high byte. Description Power-On Default 0x81 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF
1. Exceeding any of the TACH limit registers by 1 indicates that the fan is running too slowly or has stalled. The appropriate status bit is set in Interrupt Status Register 2 (0x42) to indicate fan failure. Setting the Configuration Register 1 (0x40) LOCK bit has no effect on these registers.
Table 45. Register 0x55 -- TACH1 Minimum High Byte (Power-On Default = 0xFF)
Bit No. [3:0] [7:4] Mnemonic Reserved SCADC R/W Read-only R/W Description When Bit 6 of Configuration 2 Register (0x73) is set (single-channel ADC mode), these bits are reserved. Otherwise, these bits represent Bits [3:0] of the TACH1 minimum high byte. When Bit 6 of Configuration 2 Register (0x73) is set (single-channel ADC mode), these bits are used to select the only channel from which the ADC will take measurements. Otherwise, these bits represent Bits [7:4] of the TACH1 minimum high byte. Bit Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 Single-Channel Select +2.5 VIN VCCP VCC +5 VIN +12 VIN Remote 1 temperature Local temperature Remote 2 temperature VTT IMON
Table 46. PWM Configuration Registers
Register Address 0x34 0x5C 0x5D 0x5E R/W (Note 1) R/W R/W R/W R/W PECI low limit. PWM1 configuration. PWM2 configuration. PWM3 configuration. Description Power-On Default 0x81 0x62 0x62 0x62
1. These registers become read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any subsequent attempts to write to these registers fail.
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Table 47. Register 0x5C, Register 0x5D, and Register 0x5E -- PWM1, PWM2, and PWM3 Configuration Registers (Power-On Default = 0x62)
Bit No. [2:0] Mnemonic SPIN R/W (Note 1) R/W Description These bits control the startup timeout for PWMx. The PWM output stays high until two valid TACH rising edges are seen from the fan. If there is not a valid TACH signal during the fan TACH measurement directly after the fan startup timeout period, the TACH measurement reads 0xFFFF and Interrupt Status Register 2 reflects the fan fault. If the TACH minimum high and low bytes contain 0xFFFF or 0x0000, then the Interrupt Status Register 2 bit is not set, even if the fan has not started. Bit Code 000 001 010 011 100 101 110 111 [3] [4] ALT INV R/W R/W Startup Time No startup timeout 100 ms 250 ms (default) 400 ms 667 ms 1 sec 2 sec 4 sec
Use alternative behavior setting options in Bits [7:5] below for PWMx by setting this bit to 1. Default = 0. This bit inverts the PWM output. The default is 0, which corresponds to a logic high output for 100% duty cycle. Setting this bit to 1 inverts the PWM output, so a 100% duty cycle corresponds to a logic low output. These bits assign each fan to a particular temperature sensor for localized cooling. Setting Bit 3 to Logic 1 in this register chooses whether the default of alternative behavior option is selected. Default Behavior Bits 000 = Remote 1 temperature controls PWMx (automatic fan control mode). 001 = Local temperature controls PWMx (automatic fan control mode). 010 = Remote 2 temperature controls PWMx (automatic fan control mode). 011 = PWMx runs full speed (default). 100 = PWMx disabled. 101 = Fastest speed calculated by local and Remote 2 temperature controls PWMx. 110 = Fastest speed calculated by all three temperature channel controls PWMx. 111 = Manual mode. PWM duty cycle registers (Register 0x30 to Register 0x32) become writable. Alternative Behavior Bits (Note 2) 000 = PECI0 reading controls PWMx (automatic fan control mode). 001 = PECI1 reading controls PWMx (automatic fan control mode). 010 = PECI2 reading controls PWMx (automatic fan control mode). 011 = PECI3 reading controls PWMx (automatic fan control mode). 100 = Reserved. If selected, fans run at 100% duty cycle. 101 = Fastest of all four PECI channels. Fastest speed calculated by all four PECI readings. 110 = Reserved. If selected, fans run at 100% duty cycle. 111 = Fastest speed calculated by all of the thermal zones (Local, Remote 1, Remote 2, and PECI temperatures).
[7:5]
BHVR (Note 2)
R/W
1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any subsequent attempts to write to this register fail. 2. When REPLACE mode is selected, (Register 0x36, Bit 4 set to 1) PWM1 is automatically configured for the alternative behavior setting. Register 0x36, Bits [7:5] should be set to 000 only.
Table 48. Temperature TRANGE/PWM Frequency Registers
Register Address 0x5F 0x60 0x61 R/W (Note 1) R/W R/W R/W Description Remote 1 TRANGE/PWM1 frequency. Local TRANGE/PWM2 frequency. Remote 2 TRANGE/PWM3 frequency. Power-On Default 0xC4 0xC4 0xC4
1. These registers become read-only when the Configuration Register 1 (0x40) LOCK bit is set. Any further attempts to write to these registers have no effect.
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Table 49. Register 0x5F, Register 0x60, and Register 0x61 -- Remote 1 TRANGE/PWM1 Frequency, Local TRANGE/PWM2 Frequency, and Remote 2 TRANGE/PWM3 Frequency (Power-On Default = 0xC4)
Bit No. [2:0] Mnemonic FREQ R/W (Note 1) R/W Description These bits control the PWMx frequency (only apply when PWM channel is in low frequency mode). Bit Code 000 001 010 011 100 101 110 111 [3] [7:4] HF/LF RANGE R/W R/W Frequency 11.0 Hz 14.7 Hz 22.1 Hz 29.4 Hz 35.3 Hz (default) 44.1 Hz 58.8 Hz 88.2 Hz
HF/LF = 1, high frequency PWM mode is enabled for PWMx. HF/LF = 0, low frequency PWM mode is enabled for PWMx. These bits determine the PWM duty cycle vs. the temperature range for automatic fan control. Bit Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Temperature 2C 2.5C 3.33C 4C 5C 6.67C 8C 10C 13.33C 16C 20C 26.67C 32C (default) 40C 53.33C 80C
1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set. Any further attempts to write to this register have no effect.
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Table 50. Register 0x62 -- Enhanced Acoustics Register 1 (Power-On Default = 0x00)
Bit No. [2:0] Mnemonic ACOU (Note 2) R/W (Note 1) R/W Description Assuming that PWMx is associated with the Remote 1 temperature channel, these bits define the maximum rate of change of the PWMx output for Remote 1 temperature-related changes. Instead of the fan speed jumping instantaneously to its newly determined speed, it ramps gracefully at the rate determined by these bits. This feature ultimately enhances the acoustics of the fan. When Bit 7 of Configuration Register 6 (0x10) is 0 Bit Code 000 = 1 001 = 2 010 = 3 011 = 4 100 = 8 101 = 12 110 = 24 111 = 48 Bit Code 000 = 1 001 = 2 010 = 3 011 = 4 100 = 8 101 = 12 110 = 24 111 = 48 [3] [4] EN1 SYNC R/W R/W Time for 0% to 100% 37.5 sec 18.8 sec 12.5 sec 7.5 sec 4.7 sec 3.1 sec 1.6 sec 0.8 sec Time for 0% to 100% 52.2 sec 26.1 sec 17.4 sec 10.4 sec 6.5 sec 4.4 sec 2.2 sec 1.1 sec
When Bit 7 of Configuration Register 6 (0x10) is 1
When this bit is 1, smoothing is enabled on Remote 1 temperature channel. SYNC = 1 synchronizes fan speed measurements on TACH2, TACH3, and TACH4 to PWM3. This allows up to three fans to be driven from PWM3 output and their speeds to be measured. SYNC = 0 synchronizes only TACH3 and TACH4 to PWM3 output. When the ADT7490 is in automatic fan control mode, this bit defines whether PWM1 is off (0% duty cycle) or at PWM1 minimum duty cycle when the controlling temperature is below its TMIN - hysteresis value. 0 = 0% duty cycle below TMIN - hysteresis. 1 = PWM1 minimum duty cycle below TMIN - hysteresis. When the ADT7490 is in automatic fan speed control mode, this bit defines whether PWM2 is off (0% duty cycle) or at PWM2 minimum duty cycle when the controlling temperature is below its TMIN - hysteresis value. 0 = 0% duty cycle below TMIN - hysteresis. 1 = PWM2 minimum duty cycle below TMIN - hysteresis. When the ADT7490 is in automatic fan speed control mode, this bit defines whether PWM3 is off (0% duty cycle) or at PWM3 minimum duty cycle when the controlling temperature is below its TMIN - hysteresis value. 0 = 0% duty cycle below TMIN - hysteresis. 1 = PWM3 minimum duty cycle below TMIN - hysteresis.
[5]
MIN1
R/W
[6]
MIN2
R/W
[7]
MIN3
R/W
1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any further attempts to write to this register have no effect. 2. Setting the relevant bit of Configuration Register 6 (0x10, Bits [2:0]) further decreases these ramp rates by a factor of 4.
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Table 51. Register 0x63 -- Enhanced Acoustics Register 2 (Power-On Default = 0x00)
Bit No. [2:0] Mnemonic ACOU2 R/W (Note 1) R/W Description Assuming that PWMx is associated with the local temperature channel, these bits define the maximum rate of change of the PWMx output for local temperature-related changes. Instead of the fan speed jumping instantaneously to its newly determined speed, it ramps gracefully at the rate determined by these bits. This feature ultimately enhances the acoustics of the fan. When Bit 7 of Configuration Register 6 (0x10) is 0 Bit Code 000 = 1 001 = 2 010 = 3 011 = 4 100 = 8 101 = 12 110 = 24 111 = 48 Bit Code 000 = 1 001 = 2 010 = 3 011 = 4 100 = 8 101 = 12 110 = 24 111 = 48 [3] [6:4] EN2 ACOU3 R/W R/W Time for 0% to 100% 37.5 sec 18.8 sec 12.5 sec 7.5 sec 4.7 sec 3.1 sec 1.6 sec 0.8 sec Time for 0% to 100% 52.2 sec 26.1 sec 17.4 sec 10.4 sec 6.5 sec 4.4 sec 2.2 sec 1.1 sec
When Bit 7 of Configuration Register 6 (0x10) is 1
When this bit is 1, smoothing is enabled on the local temperature channel. Assuming that PWMx is associated with the Remote 2 temperature channel, these bits define the maximum rate of change of the PWMx output for Remote 2 Temperature related changes. Instead of the fan speed jumping instantaneously to its newly determined speed, it ramps gracefully at the rate determined by these bits. This feature ultimately enhances the acoustics of the fan. When this bit is 1, smoothing is enabled on the Remote 2 temperature channel.
[7]
EN3
R/W
1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any further attempts to write to this register have no effect.
Table 52. PWM Minimum Duty Cycle Registers
Register Address 0x64 0x65 0x66 R/W (Note 1) R/W R/W R/W Description PWM1 minimum duty cycle. PWM2 minimum duty cycle. PWM3 minimum duty cycle. Power-On Default 0x80 (50% duty cycle) 0x80 (50% duty cycle) 0x80 (50% duty cycle)
1. These registers become read-only when the ADT7490 is in automatic fan control mode.
Table 53. Register 0x64, Register 0x65, and Register 0x66 -- PWM1, PWM2, and PWM3 Min Duty Cycles (Power-On Default = 0x80)
Register Address [7:0] R/W (Note 1) R/W Description These bits define the PWMMIN duty cycle for PWMx. 0x00 = 0% duty cycle (fan off). 0x40 = 25% duty cycle. 0x80 = 50% duty cycle. 0xFF = 100% duty cycle (fan full speed).
1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any further attempts to write to this register have no effect.
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Table 54. TMIN Registers (Note 1)
Register Address R/W (Note 2) R/W R/W R/W Description Remote 1 temperature TMIN. Local temperature TMIN. Remote 2 temperature TMIN. Power-On Default 0x5A (90C) 0x5A (90C) 0x5A (90C)
0x67 0x68 0x69
1. These are the TMIN registers for each temperature channel. When the temperature measured exceeds TMIN, the appropriate fan runs at minimum speed and increases with temperature according to TRANGE. 2. These registers become read-only when the Configuration Register 1 (0x40) LOCK bit is set. Any further attempts to write to these registers have no effect.
Table 55. THERM Limit Registers (Note 1)
Register Address 0x6A 0x6B 0x6C R/W (Note 2) R/W R/W R/W Description Remote 1 THERM temperature limit. Local THERM temperature limit. Remote 2 THERM temperature limit. Power-On Default 0x64 (100C) 0x64 (100C) 0x64 (100C)
1. If any temperature measured exceeds its THERM limit, all PWM outputs drive their fans at 100% duty cycle. This is a fail-safe mechanism incorporated to cool the system in the event of a critical over temperature. It also ensures some level of cooling in the event that software or hardware locks up. If set to 0x80, this feature is disabled. The PWM output remains at 100% until the temperature drops below THERM limit - hysteresis. If the THERM pin is programmed as an output, exceeding these limits by 0.25C can cause the THERM pin to assert low as an output. 2. These registers become read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any further attempts to write to these registers have no effect.
Table 56. Temperature/TMIN Hysteresis Registers
Register Address 0x6D 0x6E R/W (Note 1) R/W R/W Description Remote 1 and local temperature/TMIN hysteresis. PECI and Remote 2 temperature/TMIN hysteresis. Power-On Default 0x44 0x44
1. These registers become read-only when the Configuration Register 1(0x40) LOCK bit is set to 1. Any further attempts to write to these registers have no effect.
Table 57. Register 0x6D -- Remote 1 and Local Temperature/TMIN Hysteresis (Power-On Default = 0x44)
Bit No. (Note 1) [3:0] [7:4] Mnemonic HYSL HYSR1 R/W (Note 2) R/W R/W Description Local temperature hysteresis. 0C to 15C of hysteresis can be applied to the Local temperature AFC control loops. Remote 1 temperature hysteresis. 0C to 15C of hysteresis can be applied to the Remote 1 Temperature AFC control loops.
1. Each 4-bit value controls the amount of temperature hysteresis applied to a particular temperature channel. Once the temperature for that channel falls below its TMIN value, the fan remains running at PWMMIN duty cycle until the temperature = TMIN - hysteresis. Up to 15C of hysteresis can be assigned to any temperature channel. The hysteresis value chosen also applies to that temperature channel if its THERM limit is exceeded. The PWM output being controlled goes to 100%, if the THERM limit is exceeded and remains at 100% until the temperature drops below THERM - hysteresis. For acoustic reasons, it is recommended that the hysteresis value not be programmed less than 4C. Setting the hysteresis value lower than 4C causes the fan to switch on and off regularly when the temperature is close to TMIN. 2. These registers become read-only when the Configuration Register 1 LOCK bit is set to 1. Any further attempts to write to these registers have no effect.
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Table 58. Register 0x6E -- Remote 2 and PECI Temperature/TMIN Hysteresis (Power-On Default = 0x44)
Bit No. (Note 1) [3:0] [7:4] Mnemonic HYSP HYSR2 R/W (Note 2) R/W R/W Description PECI temperature hysteresis. 0C to 15C of hysteresis can be applied to the PECI AFC control loops. Remote 2 temperature hysteresis. 0C to 15C of hysteresis can be applied to the local temperature AFC control loops.
1. Each 4-bit value controls the amount of temperature hysteresis applied to a particular temperature channel. Once the temperature for that channel falls below its TMIN value, the fan remains running at PWMMIN duty cycle until the temperature = TMIN - hysteresis. Up to 15C of hysteresis can be assigned to any temperature channel. The hysteresis value chosen also applies to that temperature channel, if its THERM limit is exceeded. The PWM output being controlled goes to 100%, if the THERM limit is exceeded and remains at 100% until the temperature drops below THERM - hysteresis. For acoustic reasons, it is recommended that the hysteresis value not be programmed less than 4C. Setting the hysteresis value lower than 4C causes the fan to switch on and off regularly when the temperature is close to TMIN. 2. These registers become read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any further attempts to write to these registers have no effect.
Table 59. Register 0x6F -- XNOR Tree Test Enable (Power-On Default = 0x00)
Bit No. [0] [7:1] Mnemonic XEN RES R/W (Note 1) R/W R/W Description If the XEN bit is set to 1, the device enters the XNOR tree test mode. Clearing the bit removes the device from the XNOR tree test mode. Unused/reserved. Do not write to these bits.
1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any further attempts to write to this register have no effect.
Table 60. Register 0x70 -- Remote 1 Temperature Offset (Power-On Default = 0x00)
Bit No. [7:0] R/W (Note 1) R/W Description Allows a temperature offset to be automatically applied to the Remote 1 temperature channel measurement. Bit 1 of Configuration Register 5 (0x7C) determines the range and resolution of this register.
1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any further attempts to write to this register have no effect.
Table 61. Register 0x71 -- Local Temperature Offset (Power-On Default = 0x00)
Bit No. [7:0] R/W (Note 1) R/W Description Allows a temperature offset to be automatically applied to the local temperature measurement. Bit 1 of Configuration Register 5 (0x7C) determines the range and resolution of this register.
1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any further attempts to write to this register have no effect.
Table 62. Register 0x72 -- Remote 2 Temperature Offset (Power-On Default = 0x00)
Bit No. [7:0] R/W (Note 1) R/W Description Allows a temperature offset to be automatically applied to the Remote 2 temperature channel measurement. Bit 1 of Configuration Register 5 (0x7C) determines the range and resolution of this register.
1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any further attempts to write to this register have no effect.
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Table 63. Register 0x73 -- Configuration Register 2 (Power-On Default = 0x00)
Bit No. 0 1 2 3 4 5 Mnemonic FanPresDT Fan1Detect Fan2Detect Fan3Detect AVG ATTN R/W (Note 1) R/W Read-only Read-only Read-only R/W R/W Description When FanPresDT = 1, the state of Bits [3:1] of this register reflects the presence of a 4-wire fan on the appropriate TACH channel. Fan1Detect = 1 indicates that a 4-wire fan is connected to the PWM1 input. Fan2Detect = 1 indicates that a 4-wire fan is connected to the PWM2 input. Fan3Detect = 1 indicates that a 4-wire fan is connected to the PWM3 input. AVG = 1 indicates that averaging on the temperature and voltage measurements is turned off. This allows measurements on each channel to be made much faster (x16). ATTN = 1 indicates that the ADT7490 removes the attenuators from the +2.5 VIN, VCCP, +5 VIN, and +12 VIN inputs. These inputs can be used for other functions such as connecting up external sensors. It is also possible to remove attenuators from individual channels using Bits [7:4] of Configuration Register 4 (0x7D). CONV = 1 indicates that the ADT7490 is put into a single-channel ADC conversion mode. In this mode, the ADT7490 can be made to read continuously from one input only, for example, Remote 1 temperature. The appropriate ADC channel is selected by writing to Bits [7:4] of TACH1 minimum high byte register (0x55). When CONV = 1, Bits [7:4], Register 0x55 Bit Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 7 Shutdown R/W ADC Channel Selected +2.5 VIN VCCP VCC +5 VIN +12 VIN Remote 1 temperature Local temperature Remote 2 temperature VTT IMON
6
CONV
R/W
When the shutdown bit is set to 1, the ADT7490 goes into shutdown mode.
1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any further attempts to write to this register have no effect.
Table 64. Register 0x74 -- Interrupt Mask Register 1 (Power-On Default = 0x00)
Bit No. [0] [1] [2] [3] [4] [5] [6] [7] Mnemonic +2.5 VIN/ THERM VCCP VCC +5 VIN R1T LT R2T OOL R/W R/W R/W R/W R/W R/W R/W R/W R/W Description +2.5 VIN/THERM = 1 masks SMBALERT for out-of-limit conditions on the +2.5 VIN/THERM timer channel. VCCP = 1 masks SMBALERT for out-of-limit conditions on the VCCP channel. VCC = 1 masks SMBALERT for out-of-limit conditions on the VCC channel. +5 VIN = 1 masks SMBALERT for out-of-limit conditions on the +5 VIN channel. R1T = 1 masks SMBALERT for out-of-limit conditions on the Remote 1 temperature channel. LT = 1 masks SMBALERT for out-of-limit conditions on the local temperature channel. R2T = 1 masks SMBALERT for out-of-limit conditions on the Remote 2 temperature channel. OOL = 1 masks SMBALERT assertions when the OOL status bit is set. Note that the OOL mask bit is independent of the individual mask bits associated with Interrupt Status Register 2. Therefore, if the intention is to mask SMBALERT assertions for any of the Interrupt Status Register 2 bits, OOL must also be masked.
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Table 65. Register 0x75 -- Interrupt Mask Register 2 (Power-On Default = 0x00)
Bit No. [0] [1] Mnemonic +12 VIN OOL R/W R/W R/W Description When Pin 21 is configured as a +12 VIN input, +12 VIN = 1 masks SMBALERT for out-of-limit conditions on the +12 VIN channel. OOL = 1 masks SMBALERT assertions when the OOL status bit is set. Note that the OOL mask bit is independent of the individual mask bits in Interrupt Mask Register 3 (0x82). Therefore, if the intention is to mask SMBALERT assertions for any of the Interrupt Status Register 4 bits, OOL must also be masked. FAN1 = 1 masks SMBALERT for a Fan 1 fault. FAN2 = 1 masks SMBALERT for a Fan 2 fault. FAN3 = 1 masks SMBALERT for a Fan 3 fault. If Pin 14 is configured as TACH4, Fan4/ THERM = 1 masks SMBALERT for a Fan 4 fault. If Pin 14 is configured as THERM, Fan4/ THERM = 1 masks SMBALERT for an exceeded THERM timer limit. D1 = 1 masks SMBALERT for a diode open or short on a Remote 1 channel. D2 = 1 masks SMBALERT for a diode open or short on a Remote 2 channel.
[2] [3] [4] [5]
FAN1 FAN2 FAN3 Fan4/ THERM D1 FAULT D2 FAULT
R/W R/W R/W R/W
[6] [7]
R/W R/W
Table 66. Register 0x76 -- Extended Resolution Register 1 (Power-On Default = 0x00) (Note 1)
Bit No. [1:0] [3:2] [5:4] [7:6] Mnemonic +2.5 VIN VCCP VCC +5 VIN R/W Read-only Read-only Read-only Read-only Description +2.5 VIN LSBs. Holds the 2 LSBs of the 10-bit +2.5 VIN measurement. VCCP LSBs. Holds the 2 LSBs of the 10-bit VCCP measurement. VCC LSBs. Holds the 2 LSBs of the 10-bit VCC measurement. +5 VIN LSBs. Holds the 2 LSBs of the 10-bit +5 VIN measurement.
1. If this register is read, this register and the registers holding the MSB of each reading are frozen until read.
Table 67. Register 0x77 -- Extended Resolution Register 2 (Power-On Default = 0x00) (Note 1)
Bit No. [1:0] [3:2] [5:4] [7:6] Mnemonic +12 VIN TDM1 LTMP TDM2 R/W Read-only Read-only Read-only Read-only Description +12 VIN LSBs. Holds the 2 LSBs of the 10-bit +12 VIN measurement. Remote 1 temperature LSBs. Holds the 2 LSBs of the 10-bit Remote 1 temperature measurement. Local temperature LSBs. Holds the 2 LSBs of the 10-bit local temperature measurement. Remote 2 temperature LSBs. Holds the 2 LSBs of the 10-bit Remote 2 temperature measurement.
1. If this register is read, this register and the registers holding the MSB of each reading are frozen until read.
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ADT7490
Table 68. Register 0x78 -- Configuration Register 3 (Power-On Default = 0x00)
Bit No. [0] Mnemonic ALERT Enable THERM/ +2.5VIN R/W (Note 1) R/W Description ALERT = 1, Pin 10 (PWM2/ SMBALERT) is configured as an SMBALERT interrupt output to indicate out-of-limit error conditions. ALERT = 0, Pin 10 (PWM2/ SMBALERT) is configured as the PWM2 output. THERM = 1 enables THERM functionality on Pin 22 and Pin 14, if Pin 14 is configured as THERM, determined by Bit 0 and Bit 1 (Pin 14 Func) of Configuration Register 4 (0x7D). When THERM is asserted, if the fans are running and the BOOST bit is set, then the fans run at full speed. Alternatively, THERM can be programmed so that a timer is triggered to time how long THERM has been asserted. THERM = 0 enables +2.5VIN measurement on Pin 22 and disables THERM. If Bits [5:7] of Configuration Register 5 (0x7C) are set, THERM is bidirectional. If they are 0, THERM is a timer input only. Pin 14 Func (0x7D) 00 01 10 11 00 01 10 11 [2] [3] [4] BOOST FAST DC1 R/W R/W R/W THERM/+2.5 VIN (0x78) 0 0 0 0 1 1 1 1 Pin 22 +2.5 VIN +2.5 VIN +2.5 VIN +2.5 VIN THERM +2.5 VIN THERM THERM Pin 14 TACH4 TACH4 SMBALERT N/A TACH4 THERM SMBALERT N/A
[1]
R/W
When THERM is an input and BOOST = 1, assertion of THERM causes all fans to run at the maximum programmed duty cycle for fail-safe cooling. FAST = 1 enables fast TACH measurements on all channels. This increases the TACH measurement rate from once per second to once every 250 ms (4x). DC1 = 1 enables TACH measurements to be continuously made on TACH1. Fans must be driven by dc. Setting this bit prevents pulse stretching because it is not required for dc-driven motors. DC2 = 1 enables TACH measurements to be continuously made on TACH2. Fans must be driven by dc. Setting this bit prevents pulse stretching because it is not required for dc-driven motors. DC3 = 1 enables TACH measurements to be continuously made on TACH3. Fans must be driven by dc. Setting this bit prevents pulse stretching because it is not required for dc-driven motors. DC4 = 1 enables TACH measurements to be continuously made on TACH4. Fans must be driven by dc. Setting this bit prevents pulse stretching because it is not required for dc-driven motors.
[5]
DC2
R/W
[6]
DC3
R/W
[7]
DC4
R/W
1. Bits [3:0] of this register become read-only when the Configuration Register 1 LOCK (0x40) bit is set to 1. Any further attempts to write to Bits [3:0] have no effect.
Table 69. Register 0x79 -- THERM Timer Status Register (Power-On Default = 0x00)
Bit No. [0] Mnemonic ASRT/ TMR0 R/W R Description This bit is set high on the assertion of the THERM input and is cleared on read. If the THERM assertion time exceeds 45.52 ms, this bit is set and becomes the LSB of the 8-bit TMR reading. This allows THERM assertion times from 45.52 ms to 5.82 sec to be reported back with a resolution of 22.76 ms. Times how long THERM input is asserted. These seven bits read 0 until the THERM assertion time exceeds 45.52 ms.
[7:1]
TMR
R
Table 70. Register 0x7A -- THERM Timer Limit Register (Power-On Default = 0x00)
Bit No. [7:0] Mnemonic LIMT R/W R/W Description Sets maximum THERM assertion length allowed before an interrupt is generated. This is an 8-bit limit with a resolution of 22.76 ms allowing THERM assertion limits of 45.52 ms to 5.82 sec to be programmed. If the THERM assertion time exceeds this limit, Bit 5 (FAN4/THERM) of Interrupt Status Register 2 (0x42) is set. If the limit value is 0x00, an interrupt is generated immediately on the assertion of the THERM input. If THERM is configured as an output, the THERM timer limit should be set to 0xFF to avoid unwanted alerts from being generated.
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ADT7490
Table 71. Register 0x7B -- TACH Pulses per Revolution Register (Power-On Default = 0x55)
Bit No. [1:0] Mnemonic FAN1 R/W R/W Description Sets number of pulses to be counted when measuring Fan 1 speed. Can be used to determine fan pulses per revolution for unknown fan type. Bit Code 00 01 10 11 [3:2] FAN2 R/W Pulses Counted 1 2 (default) 3 4
Sets number of pulses to be counted when measuring Fan 2 speed. Can be used to determine fan pulses per revolution for unknown fan type. Bit Code 00 01 10 11 Pulses Counted 1 2 (default) 3 4
[5:4]
FAN3
R/W
Sets number of pulses to be counted when measuring Fan 3 speed. Can be used to determine fan pulses per revolution for unknown fan type. Bit Code 00 01 10 11 Pulses Counted 1 2 (default) 3 4
[7:6]
FAN4
R/W
Sets number of pulses to be counted when measuring Fan 4 speed. Can be used to determine fan pulses per revolution for unknown fan type. Bit Code 00 01 10 11 Pulses Counted 1 2 (default) 3 4
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ADT7490
Table 72. Register 0x7C -- Configuration Register 5 (Power-On Default = 0x01)
Bit No. [0] Mnemonic TWOS COMPL R/W (Note 1) R/W Description TWOS COMPL = 1 sets the temperature range to the twos complement temperature range. TWOS COMPL = 0 changes the temperature range to the Offset 64 temperature range. When this bit is changed, the ADT7490 interprets all relevant temperature register values as defined by this bit. Temp Offset = 0 sets offset range to -63C to +64C with 0.5C resolution. Temp Offset = 1 sets offset range to -63C to +127C with 1C resolution. These settings apply to Register 0x70, Register 0x71, and Register 0x72 (Remote 1, Internal, and Remote 2 Temperature offset registers. Note that PECI offset is always 1C resolution). Reserved. PECI R1 = 1 enables THERM assertions when the PECI temperature read is higher than the PECI TCONTROL limit and the THERM pin is bidirectional. If THERM is configured as an output, the THERM timer limit register (0x7A) should be set to 0xFF to avoid unwanted alerts from being generated. PECI R1 = 0 indicates that the THERM pin is configured as a timer input only. Can also be disabled by writing one of the following values to the PECI TCONTROL limit register (0x3D): Writing -64C in Offset 64 mode. Writing -128C in twos complement mode. R1 = 1 enables THERM assertions when the Remote 1 temperature read is higher than the Remote 1 THERM limit and the THERM pin is bidirectional. If THERM is configured as an output, the THERM timer limit (Register 0x7A) should be set to 0xFF to avoid unwanted alerts from being generated. R1 = 0 indicates that the THERM pin is configured as a timer input only. Can also be disabled by writing one of the following values to the Remote 1 THERM Temp Limit register (0x6A): Writing -64C in Offset 64 mode. Writing -128C in twos complement mode. [6] Local THERM Output Only R/W R1 = 1 enables THERM assertions when the Local temperature read is higher than the Local THERM limit and the THERM pin is bidirectional. If THERM is configured as an output, the THERM timer limit (Register 0x7A) should be set to 0xFF to avoid unwanted alerts from being generated. R1 = 0 indicates that the THERM pin is configured as a timer input only. Can also be disabled by writing one of the below values to the local THERM limit register (0x6B): Writing -64C in Offset 64 mode. Writing -128C in twos complement mode. R1 = 1 enables THERM assertions when the Remote 2 temperature read is higher than the Remote 2 THERM limit and the THERM pin is bidirectional. If THERM is configured as an output, the THERM timer limit (Register 0x7A) should be set to 0xFF to avoid unwanted alerts from being generated. R1 = 0 indicates that the THERM pin is configured as a timer input only. C an also be disabled by writing one of the below values to the Remote 2 THERM temperature limit register (0x6C): Writing -64C in Offset 64 mode. Writing -128C in twos complement mode.
[1]
Temp Offset
R/W
[3:2] [4]
RES PECI R1 THERM Output Only
R/W R/W
[5]
R1 THERM Output Only
R/W
[7]
R2 THERM Output Only
R/W
1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any further attempts to write to this register have no effect.
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Table 73. Register 0x7D -- Configuration Register 4 (Power-On Default = 0x00)
Bit No. [1:0] Mnemonic Pin 14 Func R/W (Note 1) R/W Description These bits set the functionality of Pin 14. 00 = TACH4 (default) 01 = THERM 10 = SMBALERT 11 = Reserved THERM Disable = 0 enables THERM overtemperature output assuming THERM is correctly configured (0x78, 0x7C, and 0x7D). THERM Disable = 1 disables THERM overtemperature output on all channels. THERM can also be disabled on any channel by: Writing -64C to the appropriate THERM temperature limit in Offset 64 mode. Writing -128C to the appropriate THERM temperature limit in twos complement mode. Max/Full on THERM = 0 indicates that fans go to 100% when THERM temperature limit is exceeded. Max/Full on THERM = 1 indicates that fans go to maximum speed (0x38, 0x39, 0x3A) when THERM temperature limit is exceeded. Bypass +2.5VIN attenuator. When set, the measurement scale for this channel changes from 0 V (0x00) to 2.25 V (0xFF). Bypass VCCP attenuator. When set, the measurement scale for this channel changes from 0 V (0x00) to 2.25 V (0xFF). Bypass +5 VIN attenuator. When set, the measurement scale for this channel changes from 0 V (0x00) to 2.25 V (0xFF). Bypass +12 VIN attenuator. When set, the measurement scale for this channel changes from 0 V (0x00) to 2.25 V (0xFF).
[2]
THERM Disable
R/W
[3]
Max/Full on THERM
R/W
[4] [5] [6] [7]
BpAtt +2.5 VIN BpAtt VCCP BpAtt +5 VIN BpAtt +12 VIN
R/W R/W R/W R/W
1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any further attempts to write to this register have no effect.
Table 74. Register 0x7E -- Manufacturer's Test Register 1 (Power-On Default = 0x00)
Bit No. [7:0] Mnemonic Reserved R/W (Note 1) Read-only Description Manufacturer's test register. These bits are reserved for manufacturer's test purposes and should not be written to under normal operation.
1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any further attempts to write to this register have no effect.
Table 75. Register 0x7F -- Manufacturer's Test Register 2 (Power-On Default = 0x00)
Bit No. [7:0] Mnemonic Reserved R/W (Note 1) Read-only Description Manufacturer's test register. These bits are reserved for manufacturer's test purposes and should not be written to under normal operation.
1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any further attempts to write to this register have no effect.
Table 76. Register 0x80 -- GPIO Configuration Register (Power-On Default = 0x00)
Bit No. [1:0] [2] [3] [4] [5] [6] [7] Mnemonic RES GPIO2 GPIO1 GPIO2 POL GPIO1 POL GPIO2 DIR GPIO1 DIR R/W Reserved R/W R/W R/W R/W R/W R/W Reserved. If GPIO2 is set to input, this register reflects the state of the pin. If GPIO2 is configured as an output, writing to this register asserts the output high or low depending on the polarity. If GPIO1 is set to input, this register reflects the state of the pin. If GPIO1 is configured as an output, writing to this register asserts the output high or low depending on the polarity. GPIO2 polarity bit. Set to 0 for active low. Set to 1 for active high. GPIO1 polarity bit. Set to 0 for active low. Set to 1 for active high. GPIO2 direction bit. Set to 1 for GPIO1 to act as an input, set to 0 for GPIO2 to act as an output. GPIO1 direction bit. Set to 1 for GPIO1 to act as an input, set to 0 for GPIO1 to act as an output. Description
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ADT7490
Table 77. Register 0x81 -- Interrupt Status Register 4 (Power-On Default = 0x00)
Bit No. [2:0] [3] Mnemonic RES PECI1 R/W Read-only Read-only Reserved. A Logic 1 indicates that the PECI high or low limit has been exceeded by the PECI value from PECI Client Address 0x31. This bit is cleared on a read of the status register only if the error condition has subsided. A Logic 1 indicates that the PECI high or low limit has been exceeded by the PECI value from PECI Client Address 0x32. This bit is cleared on a read of the status register only if the error condition has subsided. A Logic 1 indicates that the PECI high or low limit has been exceeded by the PECI value from PECI Client Address 0x33. This bit is cleared on a read of the status register only if the error condition has subsided. A Logic 1 indicates that the IMON high or low limit has been exceeded. This bit is cleared on a read of the status register only if the error condition has subsided. A Logic 1 indicates that the VTT high or low limit has been exceeded. This bit is cleared on a read of the status register only if the error condition has subsided. Description
[4]
PECI2
Read-only
[5]
PECI3
Read-only
[6] [7]
IMON VTT
Read-only Read-only
Table 78. Register 0x82 -- Interrupt Mask Register 3 (Power-On Default = 0x00) (Note 1)
Bit No. [0] [1] [2] [3] [6:4] [7] Mnemonic PECI0 DATA COMM OVT RES OOL R/W R/W R/W R/W R/W R/W R/W Description A Logic 1 masks SMBALERT assertions for out-of-limit conditions on PECI0. A Logic 1 masks SMBALERT assertions for PECI data errors. A Logic 1 masks SMBALERT assertions for PECI communications errors. OVT = 1 masks SMBALERT for overtemperature THERM conditions. Reserved. OOL = 1 masks SMBALERT assertions when the OOL status bit is set. Note that the OOL mask bit is independent of the individual mask bits of Interrupt Mask Register 4 (0x83). Therefore, if the intention is to mask SMBALERT assertions for any of the Interrupt Status Register 4 bits, OOL must also be masked.
1. If the mask bits in Register 0x82 are set, it is also necessary to set the OOL mask bit in Register 0x75 to ensure the SMBALERT output is not asserted.
Table 79. Register 0x83 -- Interrupt Mask Register 4 (Power-On Default = 0x00) (Note 1)
Bit No. [2:0] [3] [4] [5] [6] [7] Mnemonic RES PECI1 PECI2 PECI3 IMON VTT R/W R/W R/W R/W R/W R/W R/W Reserved. A Logic 1 masks ALERT assertions for out-of-limit conditions on PECI1. A Logic 1 masks ALERT assertions for out-of-limit conditions on PECI2. A Logic 1 masks ALERT assertions for out-of-limit conditions on PECI3. A Logic 1 masks ALERT assertions for out-of-limit conditions on IMON. A Logic 1 masks ALERT assertions for out-of-limit conditions on VTT. Description
1. If the mask bits in Register 0x83 are set, it is also necessary to set the OOL mask bit in Register 0x82 to ensure the SMBALERT output is not asserted.
Table 80. VTT, IMON Limit Registers
Register Address 0x84 0x85 0x86 0x87 R/W (Note 1) R/W R/W R/W R/W VTT low limit IMON low limit VTT high limit IMON high limit Description Power-On Default 0x00 0x00 0xFF 0xFF
1. These registers becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any subsequent attempts to write to these registers fail.
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ADT7490
Table 81. Register 0x88 -- PECI Configuration Register 2 (Power-On Default = 0x00)
Bit No. [2:0] [3] Mnemonic RES DOM3 R/W (Note 1) R/W R/W Reserved. CPU domain count information. Set to 0 indicates that CPU 4 associated with the PECI3 reading has a single domain (default). Set to 1 indicates that the system CPU4 contains two domains. CPU domain count information. Set to 0 indicates that CPU 3 associated with the PECI2 reading has a single domain (default). Set to 1 indicates that the system CPU3 contains two domains. CPU domain count information. Set to 0 indicates that CPU 2 associated with the PECI1 reading has a single domain (default). Set to 1 indicates that the system CPU2 contains two domains. CPU count. These bits indicate the number of CPUs in the system, which provide PECI thermal information to the ADT7490. 00 = 1 CPU (default); indicates that PECI0 data is available from CPU 1 at Address 0x30. 01 = 2 CPUs; indicates that PECI0 data is available from CPU1 at Address 0x30 and PECI1 data is available from CPU 2 at Address 0x31. 10 = 3 CPUs; indicates that PECI0 data is available from CPU1 at Address 0x30, PECI1 data is available from CPU 2 at Address 0x31 and PECI2 data is available from CPU 3 at Address 0x32. 11 = 4 CPUs; indicates that PECI0 data is available from CPU1 at Address 0x30, PECI1 data is available from CPU 2 at Address 0x31, PECI2 data is available from CPU 3 at Address 0x32 and PECI3 data is available from CPU 4 at Address 0x33. Description
[4]
DOM2
R/W
[5]
DOM1
R/W
[7:6]
#CPU
R/W
1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any subsequent attempts to write to this register fail.
Table 82. Operating Point Registers (Note 1 and 2)
Register Address 0x8A 0x8B 0x8C 0x8D R/W (Note 3) R/W R/W R/W R/W Description PECI operating point register. Remote 1 operating point register (default = 100C). Local temperature operating point register (default = 100C). Remote 2 operating point register (default = 100C). Power-On Default 0xFB 0x64 0x64 0x64
1. These registers set the target operating point for each temperature channel when the dynamic TMIN control feature is enabled. 2. The fans being controlled are adjusted to maintain temperature about an operating point. 3. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any subsequent attempts to write to this register fail.
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ADT7490
Table 83. Register 0x8E -- Dynamic TMIN Control Register 1 (Power-On Default = 0x00)
Bit No. [0] Mnemonic CYR2 R/W (Note 1) R/W Description MSB of 3-bit Remote 2 Cycle Value. The other two bits of the code reside in Dynamic TMIN Control Register 2 (0x8F). These three bits define the delay time between making subsequent TMIN adjustments in the control loop in terms of the number of monitoring cycles. The system has associated thermal time constants that need to be found to optimize the response of fans and the control loop. VCCPLO = 1. When the power is supplied from 3.3 V STANDBY and the core voltage (VCCP) drops below its VCCP low limit value (0x46), the following occurs: Status Bit 1 in Status Register 1 is set. SMBALERT is generated, if enabled. PROCHOT monitoring is disabled. Dynamic TMIN control is disabled. The device is prevented from entering shutdown. Everything is re-enabled once VCCP increases above the VCCP low limit. PHTR1 = 1 copies the Remote 1 current temperature to the Remote 1 operating point register if THERM is asserted. The operating point contains the temperature at which THERM is asserted, allowing the system to run as quietly as possible without affecting system performance. PHTR1 = 0 ignores any THERM assertions on the THERM pin. The Remote 1 operating point register reflects its programmed value. PHTL = 1 copies the local channel's current temperature to the local operating point register if THERM is asserted. The operating point contains the temperature at which THERM is asserted. This allows the system to run as quietly as possible without affecting system performance. PHTL = 0 ignores any THERM assertions on the THERM pin. The local temperature operating point register reflects its programmed value. PHTR2 = 1 copies the Remote 2 current temperature to the Remote 2 operating point register if THERM is asserted. The operating point contains the temperature at which THERM is asserted, allowing the system to run as quietly as possible without affecting system performance. PHTR2 = 0 ignores any THERM assertions on the THERM pin. The Remote 2 operating point register reflects its programmed value. R1T = 1 enables dynamic TMIN control on the Remote 1 temperature channel. The chosen TMIN value is dynamically adjusted based on the current temperature, operating point, and high and low limits for this zone. R1T = 0 disables dynamic TMIN control. The TMIN value chosen is not adjusted, and the channel behaves as described in the section. LT = 1 enables dynamic TMIN control on the local temperature channel. The chosen TMIN value is dynamically adjusted based on the current temperature, operating point, and high and low limits for this zone. LT = 0 disables dynamic TMIN control. The TMIN value chosen is not adjusted, and the channel behaves as described in the Automatic Fan Control Overview section. R2T = 1 enables dynamic TMIN control on the Remote 2 temperature channel. The chosen TMIN value is dynamically adjusted based on the current temperature, operating point, and high and low limits for this zone. R2T = 0 disables dynamic TMIN control. The TMIN value chosen is not adjusted, and the channel behaves as described in the Automatic Fan Control Overview section.
[1]
VCCPLO
R/W
[2]
PHTR1
R/W
[3]
PHTL
R/W
[4]
PHTR2
R/W
[5]
R1T
R/W
[6]
LT
R/W
[7]
R2T
R/W
1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any subsequent attempts to write to this register fail.
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ADT7490
Table 84. Register 0x8F -- Dynamic TMIN Control Register 2 (Power-On Default = 0x00)
Bit No. [2:0] Mnemonic CYR1 R/W (Note 1) R/W Description 3-Bit Remote 1 Cycle Value. These three bits define the delay time between making subsequent TMIN adjustments in the control loop for the Remote 1 channel in terms of number of monitoring cycles. The system has associated thermal time constants that need to be found to optimize the response of fans and the control loop. Bit Code 000 001 010 011 100 101 110 111 [5:3] CYL R/W Decrease Cycle 8 cycles (1 sec) 16 cycles (2 sec) 32 cycles (4 sec) 64 cycles (8 sec) 128 cycles (16 sec) 256 cycles (32 sec) 512 cycles (64 sec) 1024 cycles (128 sec) Increase Cycle 16 cycles (2 sec) 32 cycles (4 sec) 64 cycles (8 sec) 128 cycles (16 sec) 256 cycles (32 sec) 512 cycles (64 sec) 1024 cycles (128 sec) 2048 cycles (256 sec)
3-Bit Local Temperature Cycle Value. These three bits define the delay time between making subsequent TMIN adjustments in the control loop for the local temperature channel in terms of number of monitoring cycles. The system has associated thermal time constants that need to be found to optimize the response of fans and the control loop. Bit Code 000 001 010 011 100 101 110 111 Decrease Cycle 8 cycles (1 sec) 16 cycles (2 sec) 32 cycles (4 sec) 64 cycles (8 sec) 128 cycles (16 sec) 256 cycles (32 sec) 512 cycles (64 sec) 1024 cycles (128 sec) Increase Cycle 16 cycles (2 sec) 32 cycles (4 sec) 64 cycles (8 sec) 128 cycles (16 sec) 256 cycles (32 sec) 512 cycles (64 sec) 1024 cycles (128 sec) 2048 cycles (256 sec)
[7:6]
CYR2
R/W
2 LSBs of 3-Bit Remote 2 Cycle Value. The MSB of the 3-bit code resides in the Dynamic TMIN Control Register 1 (Register 0x8E). These three bits define the delay time between making subsequent TMIN adjustments in the control loop for the Remote 2 channel in terms of number of monitoring cycles. The system has associated thermal time constants that need to be found to optimize the response of fans and the control loop. Bit Code 000 001 010 011 100 101 110 111 Decrease Cycle 8 cycles (1 sec) 16 cycles (2 sec) 32 cycles (4 sec) 64 cycles (8 sec) 128 cycles (16 sec) 256 cycles (32 sec) 512 cycles (64 sec) 1024 cycles (128 sec) Increase Cycle 16 cycles (2 sec) 32 cycles (4 sec) 64 cycles (8 sec) 128 cycles (16 sec) 256 cycles (32 sec) 512 cycles (64 sec) 1024 cycles (128 sec) 2048 cycles (256 sec)
1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any subsequent attempts to write to this register fail.
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ADT7490
Table 85. Register 0x90 -- Dynamic TMIN Control Register 3 (Power-On Default = 0x00)
Bit No. [2:0] [5:3] Mnemonic RES CYP R/W (Note 1) Reserved R/W Reserved 3-Bit PECI Temperature Cycle Value. These three bits define the delay time between making subsequent TMIN adjustments in the control loop for the PECI temperature channels in terms of number of monitoring cycles. The system has associated thermal time constants that need to be found to optimize the response of fans and the control loop. Bit Code 000 001 010 011 100 101 110 111 [6] PHTP R/W Decrease Cycle 8 cycles (1 sec) 16 cycles (2 sec) 32 cycles (4 sec) 64 cycles (8 sec) 128 cycles (16 sec) 256 cycles (32 sec) 512 cycles (64 sec) 1024 cycles (128 sec) Increase Cycle 16 cycles (2 sec) 32 cycles (4 sec) 64 cycles (8 sec) 128 cycles (16 sec) 256 cycles (32 sec) 512 cycles (64 sec) 1024 cycles (128 sec) 2048 cycles (256 sec) Description
PHTR1 = 1 copies the PECI0 current reading to the PECI operating point register if THERM is asserted. The operating point contains the temperature at which THERM is asserted, allowing the system to run as quietly as possible without affecting system performance. PHTR1 = 0 ignores any THERM assertions on the THERM pin. The PECI operating point register reflects its programmed value. PECI = 1 enables dynamic TMIN control on the PECI temperature channel. The chosen TMIN value is dynamically adjusted based on the current temperature, operating point, and high and low limits for this zone. PECI = 0 disables dynamic TMIN control. The TMIN value chosen is not adjusted and the channel behaves as described in the Automatic Fan Control Overview section.
[7]
PECI
R/W
1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any subsequent attempts to write to this register fail.
Table 86. Register 0x94 -- PECI0 Temperature Offset (Power-On Default = 0x00)
Bit No. [7:0] R/W (Note 1) R/W Description Allows a temperature offset to be automatically applied to the PECI0 channel measurements. The programmable offset range is from -63C to +127C with 1C resolution.
1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any further attempts to write to this register have no effect.
Table 87. Register 0x95 -- PECI1 Temperature Offset (Power-On Default = 0x00)
Bit No. [7:0] R/W (Note 1) R/W Description Allows a temperature offset to be automatically applied to the PECI1 channel measurements. The programmable offset range is from -63C to +127C with 1C resolution.
1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any further attempts to write to this register have no effect.
Table 88. Register 0x96 -- PECI2 Temperature Offset (Power-On Default = 0x00)
Bit No. [7:0] R/W (Note 1) R/W Description Allows a temperature offset to be automatically applied to the PECI2 channel measurements. The programmable offset range is from -63C to +127C with 1C resolution.
1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any further attempts to write to this register have no effect.
Table 89. Register 0x97 -- PECI3 Temperature Offset (Power-On Default = 0x00)
Bit No. [7:0] R/W (Note 1) R/W Description Allows a temperature offset to be automatically applied to the PECI3 channel measurements. The programmable offset range is from -63C to +127C with 1C resolution.
1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any further attempts to write to this register have no effect.
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ADT7490
ORDERING INFORMATION
Device Order Number* ADT7490ARQZ ADT7490ARQZ-REEL ADT7490ARQZ-R7 24-Lead QSOP RQ-24 Package Type Package Option Shipping 56 Tube 2500 Tape & Reel 1000 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *These are Pb-Free packages.
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ADT7490
PACKAGE DIMENSIONS
QSOP24 NB CASE 492B-01 ISSUE A
2X
0.20 C D D
24
A
D
13
C
GAUGE PLANE
L2
E1
2X
E
L DETAIL A
2X 12 TIPS
C
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. 4. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.15 PER SIDE. D AND E1 ARE DETERMINED AT DATUM H. 5. DATUMS A AND B ARE DETERMINED AT DATUM H. DIM A A1 b C D E E1 e h L L2 M MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.20 0.30 0.19 0.25 8.65 BSC 6.00 BSC 3.90 BSC 0.635 BSC 0.22 0.50 0.40 1.27 0.25 BSC 0_ 8_
0.20 C D
1 12 24X
e 0.10 C
B
b 0.25
0.25 C D
M
C A-B D A H
h x 45 _
0.10 C
24X
A1
C
SEATING PLANE
DETAIL A
M
SOLDERING FOOTPRINT*
0.42 24 13
24X
1.12
24X
6.40
1 0.635 PITCH
12
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
dBCOOL is a registered trademarks of Semiconductor Components Industries, LLC (SCILLC). Pentium is a registered trademark of Intel Corporation.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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ADT7490/D

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